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Original question:
Part Number: PROCESSOR-SDK-AM335X
Tool/software:
We are running into issue w.r.t splash screen in uboot. And in this post (e2e.ti.com/.../processor-sdk-am335x-splash-screen-in-u-boot) there is a mention that it is being worked on by TI...
Any updates on this?
regards
Karthik
I tried on the latest 9.3.5.2 release.
And the uboot image crashes for our board:
U-Boot SPL 2023.04 (Jan 09 2025 - 01:27:30 -0800) Trying to boot from NAND Loading Environment from nowhere... OK <debug_uart> U-Boot 2023.04 (Jan 09 2025 - 01:27:30 -0800) CPU : AM335X-GP rev 2.1 Model: Tek AM335x trebfp DRAM: 1 GiB Video device 'lcdc@0' cannot allocate frame buffer memory -ensure the device is set up before relocation Error binding driver 'tilcdc': -28 Some drivers failed to bind Error binding driver 'ti_sysc': -28 Some drivers failed to bind Error binding driver 'simple_bus': -28 Some drivers failed to bind Error binding driver 'simple_bus': -28 Some drivers failed to bind Error binding driver 'simple_bus': -28 Some drivers failed to bind initcall sequence bffdb838 failed at call ### ERROR ### Please RESET the board ###
/*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#define TREB_FP 1
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TI AM335x Treb FP";
compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
chosen {
stdout-path = &uart0;
tick-timer = &timer2;
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 0>;
brightness-levels = <188 198 204 213 222 230 239 248 255>;
default-brightness-level = <7>;
};
panel {
compatible = "ti,tilcdc,panel";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mylcdc1_pins_default>;
backlight = <&backlight>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
480x128p62 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <128>;
hfront-porch = <8>;
hback-porch = <43>;
hsync-len = <4>;
vback-porch = <12>;
vfront-porch = <8>;
vsync-len = <4>;
hsync-active = <1>;
vsync-active = <1>;
};
};
port {
panel_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_default>;
LCD_ON_OFF {
label = "lcd_on_off";
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
slot2_b {
label = "slot2_b";
gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
};
slot2_g {
label = "slot2_g";
gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
slot3_b {
label = "slot3_b";
gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
};
slot2_r {
label = "slot2_r";
gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
};
interlock_r {
label = "interlock_r";
gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
};
slot3_g {
label = "slot3_g";
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
};
slot3_r {
label = "slot3_r";
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
};
lan_status {
label = "lan_status";
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
};
interlock_g {
label = "interlock_g";
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
};
slot1_b {
label = "slot1_b";
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
};
slot1_g {
label = "slot1_g";
gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
};
slot1_r {
label = "slot1_r";
gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
};
};
rotary {
compatible = "rotary-encoder";
pinctrl-names = "default";
pinctrl-0 = <&rotar_pins_default>;
gpios = <&gpio0 0 0>, <&gpio0 1 0>;
rotary-encoder,relative-axis;
linux,axis = <1>; /* REL_Y */
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&io_pins_default>;
lan_reset {
label = "lan_reset";
gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
linux,code = <0x101>;
};
rotary_pb {
label = "rotary_pb";
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
linux,code = <28>;
};
};
};
&am33xx_pinmux {
mydebugss1_pins_default: mydebugss1-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9d0, PIN_INPUT | MUX_MODE0) /* (C11) TMS.TMS */
AM33XX_IOPAD(0x9d4, PIN_INPUT | MUX_MODE0) /* (B11) TDI.TDI */
AM33XX_IOPAD(0x9d8, PIN_OUTPUT | MUX_MODE0) /* (A11) TDO.TDO */
AM33XX_IOPAD(0x9dc, PIN_INPUT | MUX_MODE0) /* (A12) TCK.TCK */
AM33XX_IOPAD(0x9e0, PIN_INPUT | MUX_MODE0) /* (B10) nTRST.nTRST */
AM33XX_IOPAD(0x9e4, PIN_INPUT | MUX_MODE0) /* (C14) EMU0.EMU0 */
AM33XX_IOPAD(0x9e8, PIN_INPUT | MUX_MODE0) /* (B14) EMU1.EMU1 */
AM33XX_IOPAD(0x9b0, PIN_INPUT | MUX_MODE6) /* (A15) xdma_event_intr0.EMU2 */
AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6) /* (D14) xdma_event_intr1.EMU3 */
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE6) /* (C15) spi0_cs1.EMU4 */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
>;
};
test_pins_default: test-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x854, PIN_INPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] */
>;
};
rotar_pins_default: rotar-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE7) /* (M17) mdio_data.gpio0[0] */
AM33XX_IOPAD(0x94c, PIN_INPUT | MUX_MODE7) /* (M18) mdio_clk.gpio0[1] */
>;
};
io_pins_default: io-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x944, PIN_INPUT | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] */
AM33XX_IOPAD(0x994, PIN_INPUT | MUX_MODE7) /* (B13) mcasp0_fsx.gpio3[15] */
>;
};
ts_pins: ts_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] */
AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
>;
};
led_pins_default: led-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] */
AM33XX_IOPAD(0x908, PIN_OUTPUT | MUX_MODE7) /* (H16) gmii1_col.gpio3[0] */
AM33XX_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* (H17) gmii1_crs.gpio3[1] */
AM33XX_IOPAD(0x910, PIN_OUTPUT | MUX_MODE7) /* (J15) gmii1_rxer.gpio3[2] */
AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE7) /* (J16) gmii1_txen.gpio3[3] */
AM33XX_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] */
AM33XX_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* (L17) gmii1_rxd3.gpio2[18] */
AM33XX_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* (L16) gmii1_rxd2.gpio2[19] */
AM33XX_IOPAD(0x93c, PIN_OUTPUT | MUX_MODE7) /* (L15) gmii1_rxd1.gpio2[20] */
AM33XX_IOPAD(0x940, PIN_OUTPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */
AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLUP | MUX_MODE7) /* (J17) gmii1_rxdv.gpio3[4] */
>;
};
nand_pins_default: nand-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* (T9) gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* (R9) gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* (V8) gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* (U8) gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* (T8) gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* (R8) gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* (V7) gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* (U7) gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* (T17) gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* (U17) gpmc_wpn.gpmc_wpn */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* (V6) gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* (R7) gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* (T7) gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* (U6) gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
myi2c1_pins_default: myi2c1-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3) /* (E17) uart0_rtsn.I2C1_SCL */
AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3) /* (E18) uart0_ctsn.I2C1_SDA */
>;
};
mylcdc1_pins_default: mylcdc1-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* (U5) lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* (R5) lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* (V5) lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* (R6) lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* (R1) lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* (R2) lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* (R3) lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* (R4) lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* (T1) lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* (T2) lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* (T3) lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* (T4) lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* (U1) lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* (U2) lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* (U3) lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* (U4) lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* (V2) lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* (V3) lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* (V4) lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* (T5) lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* (U13) gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* (V13) gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* (R12) gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* (T12) gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* (U12) gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* (T11) gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* (T10) gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* (U10) gpmc_ad8.lcd_data23 */
>;
};
myspi1_pins_default: myspi1-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
AM33XX_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
>;
};
myuart1_pins_default: myuart1-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */
>;
};
myuart2_pins_default: myuart2-default-pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&myuart1_pins_default>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&myuart2_pins_default>;
status = "okay";
};
&epwmss0 {
status = "okay";
ecap0: pwm@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
};
};
&lcdc {
status = "okay";
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&panel_0>;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&myi2c1_pins_default>;
status = "okay";
clock-frequency = <100000>;
touchscreen@38 {
compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&ts_pins>;
touchscreen-size-x = <480>;
touchscreen-size-y = <128>;
interrupt-parent = <&gpio3>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
};
};
&tscadc {
status = "okay";
adc {
ti,adc-channels = <0 2 3>;
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "peripheral";
};
&elm {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_pins_default>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000C0000 0x00200000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x002C0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x002E0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00300000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00B00000 0xF500000>;
};
};
};
Hi,
Please refer to the following: https://software-dl.ti.com/processor-sdk-linux/esd/AM335X/09_03_05_02/exports/docs/linux/Foundational_Components/U-Boot/Apps-Splash-Screen.html and the following patches: https://git.ti.com/cgit/ti-u-boot/ti-u-boot/log/?h=ti-u-boot-2023.04&qt=author&q=Sukrut+Bellary
Regards,
Krunal
I did follow that exact document on uboot splash screen
and also got uboot source pointing to this tag:https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tag/?h=09.03.05
and i verified i have changes u are pointing at.
and searching for the error message i get this code:
if (addr < gd->video_bottom) {
/* Device tree node may need the 'bootph-all' or
* 'bootph-some-ram' tag
*/
printf("Video device '%s' cannot allocate frame buffer memory -ensure the device is set up before relocation\n",
dev->name);
return -ENOSPC;
}After including the am335x-evm-u-boot.dtsi in my dts which adds the "bootph-all" to many nodes i was able to get around the issue.
And also able to run this command "bmp display $loadaddr m m" without any errors
BUT
no display, we debugged a little with print statements and are speculating it could be because of backlight.
same dts works on linux.
Hi,
Thanks for the update! We have the following patch for backlight:
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04&id=2a13324ec63cc488f5f578886d0cf6ece348dfda
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04&id=6b6f668489b43682d4052a273376175a67314081
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04&id=b7da29eeaddecc6c6d9b422b8385cac6f6bcce55
Regards,
Krunal
Thanks for all the support, we were missing the board changes that adds lcd_pin_mux; because we used an older evm board files as reference which doesnot have the lcd changes in them.
we added lcd_pin_mux and configure_module_pin_mux(lcd_pin_mux) call to get the uboot splash screen working.