Original question:
Tool/software:
HI
I would like to continue where the following thread left off. I would like to get the PRU running at 333MHZ in AM625. I can provide feedback and testing.
Thank you
The PRU instructions are being ran at 333 Mhz with the settings above. However, the following instructions with default settings (250Mhz) was taking ~600ns. With the proposed 333Mhz clock settings the instructions are taking over 3us. Seems the proposed settings affects the DDR read speed. Hoping it does as I would like to decrease the 600ns read if possible.
set R30,R30,PRU_TEST_1 NOP clr R30,R30,PRU_TEST_1 LBBO &r5, ddr_mapped_addr,0,50 set R30,R30,PRU_TEST_1 NOP clr R30,R30,PRU_TEST_1
DDR 50 byte read timing with "Default 250 Mhz" settings
DDR 50 byte read timing with "333Mhz proposed settings"
Hello Daniel & D Anthony,
Are you on the same team?
Your clock frequency settings do NOT look correct
Step 1: please test with using ICLK WITHOUT setting frequency
Taking another look at the clock settings in this thread, they do NOT look correct to me. ICLK is a fixed 250MHz clock, so you should NOT manually set the frequency. If you are using ICLK, you should do it like this:
https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/arch/arm64/boot/dts/ti/k3-am62-main.dtsi?h=ti-linux-6.6.y-cicd&id=34e6b1d215aae3e5d9c9d455edc943140ec99775
My best guess is that Linux is selecting a different clock source than ICLK and setting that other clock source to 250MHz. Thus, even though you have a 250MHz clock, it is a different 250MHz clock than the bus clock, and thus you still get lowered read/write performance.
Step 2: ok, how SHOULD we be setting the clock frequency if we want something other than 250MHz?
This is a bit tricky, since the AM62x TRM clock diagram is wrong right now. However, the clock diagram for AM64x should be similar. Let's take a look at the clock sources:
I have highlighted the paths we care about.
The PRU core clocks (CORE_CLK in the image) have 2 possible sources: pruss_iclk, and pruss_core_clk.
pruss_iclk (or ICLK) is a fixed 250MHz. This is the "bus interface clock" or VCLK which used to communicate with the rest of the processor. As you can see in the diagram, this clock source can also be routed to the PRU's internal CORE_CLK. I would NOT expect you to see extra read/write latencies with this clock.
pruss_core_clk (or ICSSG0_CORE_CLK in the image) has 2 different clock sources that go into it: MAIN_2_HSDIVOUT0_CLK and MAIN_0_HSDIVOUT9_CLK. These clock sources can be configured to have different frequencies. You should ONLY be setting the clock frequency if you are selecting one of these clock sources that will be routed through pruss_core_clk.
Let's check the PRU clock IDs that are defined in the TISCI documentation. Look under ICSSM0 (even though AM62x has PRUSS, NOT PRU-ICSS):
https://software-dl.ti.com/tisci/esd/09_02_07/5_soc_doc/am62x/clocks.html#clocks-for-icssm0-device
For pruss_core_clk / CORE_CLK, we need to use clock ID 0, and list either clock ID 1 or 2 as an input:
For pruss_iclk / VCLK, we use only clock ID 14:
Step 3: ok, so what SHOULD my clock settings look like?
We already know what it should look like if using ICLK: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/arch/arm64/boot/dts/ti/k3-am62-main.dtsi?h=ti-linux-6.6.y-cicd&id=34e6b1d215aae3e5d9c9d455edc943140ec99775
So let's focus on using pruss_core_clk to get other frequencies.
Please follow the concepts of the FAQ here. It is for ICSSG instead of PRUSS, but similar concepts:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1049800/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-linux
I'll ask Nitika to followup with exactly which frequencies are supported for each clock source. So this code might NOT have the correct frequencies now. But let's pretend that MAIN_0_HSDIVOUT9_CLK can output 200MHz.
Then in order to set the PRU core clocks to 200MHz, I would expect the code to look like this:
pruss_coreclk_mux: coreclk-mux@3c {
reg = <0x3c>;
#clock-cells = <0>;
clocks = <&k3_clks 81 0>, /* pruss_core_clk */
<&k3_clks 81 14>; /* pruss_iclk */
assigned-clocks = <&k3_clks 81 0>, <&pruss_coreclk_mux>;
assigned-clock-parents = <&k3_clks 81 2>, <&k3_clks 81 0>; /* DEV_ICSSM0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK */
assigned-clock-rates = <200000000>, <0>; /* 200MHz */
};
Please let us know if this works for you. We will use this interaction to create a new e2e FAQ and new documentation for the AM62x clock.
Regards,
Nick
For the 250Mhz, I'm using:
pruss_coreclk_mux: coreclk-mux@3c {
reg = <0x3c>;
#clock-cells = <0>;
clocks = <&k3_clks 81 0>, /* pruss_core_clk */
<&k3_clks 81 14>; /* pruss_iclk */
assigned-clocks = <&pruss_coreclk_mux>;
assigned-clock-parents = <&k3_clks 81 14>;
};
and for 200Mhz and 333Mhz, I'm using:
pruss_coreclk_mux: coreclk-mux@3c {
reg = <0x3c>;
#clock-cells = <0>;
clocks = <&k3_clks 81 0>, /* pruss_core_clk */
<&k3_clks 81 14>; /* pruss_iclk */
assigned-clocks = <&k3_clks 81 0>, <&pruss_coreclk_mux>;
assigned-clock-parents = <&k3_clks 81 2>, <&k3_clks 81 0>; /* DEV_ICSSM0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK */
assigned-clock-rates = <200000000>, <0>; /* 200MHz */
};
(just updating the clock-rate for 333Mhz)
This results in timings that look like:
And the code I'm using:
RESET_PRU_CLOCK r8, r9
LDI32 r8, 0x70000000 // OCSRAM
LDI r9, 1024
LOOP TEST_OCSRAM_DONE, r9
LBBO &r10, r8, 0, 32
ADD r8, r8, 32
TEST_OCSRAM_DONE:
GET_PRU_CLOCK r8, r9, 4
SBCO &r8, CONST_PRUDRAM, 16, 4
RESET_PRU_CLOCK r8, r9
LDI32 r8, 0x0005040000 // M4 DRAM
LDI r9, 1024
LOOP TEST_M4_DONE, r9
LBBO &r10, r8, 0, 32
ADD r8, r8, 32
TEST_M4_DONE:
GET_PRU_CLOCK r8, r9, 4
SBCO &r8, CONST_PRUDRAM, 24, 4
RESET_PRU_CLOCK r8, r9
LDI32 r8, 0x8f000000 // DDR DRAM (reserved)
LDI r9, 1024
LOOP TEST_DDR_DONE, r9
LBBO &r10, r8, 0, 32
ADD r8, r8, 32
TEST_DDR_DONE:
GET_PRU_CLOCK r8, r9, 4
SBCO &r8, CONST_PRUDRAM, 32, 4
RESET_PRU_CLOCK r8, r9
LDI32 r8, 0x00010000 // local shared ram
LDI r9, 1024
LOOP TEST_SHARED_DONE, r9
LBBO &r10, r8, 0, 32
ADD r8, r8, 32
TEST_SHARED_DONE:
GET_PRU_CLOCK r8, r9, 4
SBCO &r8, CONST_PRUDRAM, 40, 4
I can then use devmem2 to query the four values from the PRU's ram.
Hi Daniel,
I'll ask Nitika to followup with exactly which frequencies are supported for each clock source. So this code might NOT have the correct frequencies now.
As Nick mentioned above, please find the frequencies can be used with each of the PLL clock sources:
PLL2 (Parent Clock ID 1) : 225 and 300MHz
PLL0 (Parent Clock ID 2) : 200, 250 and 333 MHz
Regards,
Nitika