AM1808 EMIFA access width versus bus master priority

I have a question that I couldn't answer by reading the EMIFA and AM1808 documents (or maybe I was not reading carefully enough!)

Let's say I use the EMIFA to interface with a16-bit device.

If the ARM makes a 32-bit read in the EMIFA address space, the EMIFA makes two consecutive read cycles on the external device and returns a 32-bit value to the ARM.

Now my question:

Can an access in the EMIFA address space by a bus master of a higher priority (DMA for example) occur between the two reads required to complete the 32-bit read of the ARM ?

Regards,

Michel