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AM62D-Q1: The AM62D-Mcasp interface configuration

tian mei
Prodigy 80 points

Part Number: AM62D-Q1

Tool/software:

Hi TI's expert，

During the power-on process and initialization process of the AM62D chip, including during reset, is there a way for us to configure each pin of the audio Mcasp interface to output 0-level signal or Hi-Z?

Tks.

  • 0
    TI__Guru**** 180656 points

    Hi Tian,

    India has a holiday today, please expect delayed response from the domain expert.

  • 0 in reply to Bin Liu
    TI__Guru**** 226115 points

    Hello Tian Mei, 

    Thank you for the query.

    Most of the McASP signals during reset are configured as GPIOs.

    During reset and after reset the TX and RX buffers are off. The internal pulls are disabled.

    The IOs are effectively in high-z state. 

    The IOs can be configured only after the ROM boot is complete and the software is running.

    In case you would want any of these IOs to be in a know state during reset and after reset, an external pull is recommended.

    During the operation in case any of these IOs could float, an external pull is recommended.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 80 points

    Hi Sreenivasa,

    Thank you for your reply. We conducted an experiment in the past two days and actually measured the level of a pin on McASP interface to be about 0.48v on our AM275 board when power on and reset. After reset we configured the IO pull down,so the level of pin would be 0v.Do you think this 0.48v level is normal? 

    And why does this pin have an output level of 0.48v?

    TKS.

  • 0 in reply to tian mei
    TI__Guru**** 226115 points

    Hello Tian Mei, 

    Thank you for the inputs.

    Please help me understand if the query is for AM62D-Q1 or AM275?

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 80 points

    Hi Sreenivasa,

    Since we have not obtained the AM62D demo board yet, so we conducted the verification on the existing AM275 board. However we are not sure whether the performance of the AM62D will be the same as the AM275.

    Tks.

  • 0 in reply to tian mei
    TI__Guru**** 226115 points

    Hello Tian Mei, 

    Thank you.

    Please refer to below section of the Am62D-Q1 data sheet 

    6.8.6 LVCMOS Electrical Characteristics

    IIN (2) Input Leakage Current. VI = 1.8V 10 µA VI = 0V -10 µA

    (2) This parameter defines leakage current when the terminal is operating as an input, undriven output, or both input and undriven output, without internal pulls enabled

    tian mei said:
    Thank you for your reply. We conducted an experiment in the past two days and actually measured the level of a pin on McASP interface to be about 0.48v on our AM275 board when power on and reset. After reset we configured the IO pull down,so the level of pin would be 0v.Do you think this 0.48v level is normal? 

    Is this an observation or do you have some concerns?

    Regards,

    Sreenivasa

  • +1 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 226115 points

    Hello Tian Mei, 

    Refer below additional inputs

    Voltage on an unconnected AM62Dx pin is possible. The voltage observed on the pin is the result of leakage paths in the IO buffer, where the leakage can be as much as 10uA to either VSS or VDDSHV. This is normal as long as the leakage is not greater than 10uA. The resulting mid-supply voltage is not a problem for the AM62Dx device as long as the receiver (input buffer) in the IO buffer remains off. However, the pin must be driven or pulled to a valid logic level anytime the receiver is turned on. Never allow the input of an enabled input buffer in the AM62Dx device to float.

    Note: We recommend external pulls to be used on any signal that connects AM62Dx to the input of another device. The external pull is needed to hold the signal in a valid logic state until software turns on the associated AM62Dx IO buffer such that it drives the signal to a valid logic state.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 80 points

    Hi Sreenivasa,

    Thank you for your support. It is very helpful for us.

    Tks.

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 80 points

    Hi Sreenivasa,

    As the datasheet mentioned, if the leakage current is less than 10uA,so the leakage voltage should not be 0.48v. Is this right?

    Tks.

  • 0 in reply to tian mei
    TI__Guru**** 226115 points

    Hello Tian Mei, 

    tian mei said:
    As the datasheet mentioned, if the leakage current is less than 10uA,so the leakage voltage should not be 0.48v. Is this right?

    That is correct. The voltage depends on the leakage and the IO supply.

    Regards,

    Sreenivasa