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Original question:

DRA829J-Q1: PCIe Receiver Detection

DRA829J-Q1: PCIe Receiver Detection

Peter Fritzenschaft
Intellectual 361 points
Part Number: DRA829J-Q1

Tool/software:

Hello, 

we are using DRA829J-Q1 as PCIe Root Complex connected to an Artix UltraScale+ as Endpoint.

The UltraScale Datasheet states that dynamic switching of the receiver termination mode is required when the remote transmitter is using the falling edge for the receiver detection.

In the Jacinto documentation i cannot find something about the receiver detection edge.

Does the Jacinto use rising or falling edge for Receiver Detection?

Kind regards, Peter

  • 0
    TI__Guru 50633 points

    Hi Peter,

    The PCIe subsystem is designed in compliance to PCIe® Base Specification, Revision 4.0 (Version 0.7). Based on this specification, the Receiver Detection sequence is to quote:

    1. A Transmitter must start at a stable voltage prior to the detect common mode
      shift.
    2. A Transmitter changes the common mode voltage on D+ and D- consistent with
      meeting the VTX-RCV-DETECT parameter and consistent with detection of Receiver
      high impedance which is bounded by parameters ZRX -HIGH-IMP-DC-POS, ZRX-HIGH-IMP-
      DC-NEG in Table 9-9. Receiver is detected based on the rate that the lines change to
      the new voltage.

    I assumed this meant PCIe devices typically use the rate at which voltage rises to determine if a lane is in-use instead of edge.

    Regards,

    Takuma