Hi
I have a couple questions about the cache for the Cortex-M3 in the ducati module of the TI814x.
In my *.cfg file, I've enabled the AMMU and cache with the following SYS/BIOS settings
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Cache.configureCache = true; AMMU.largePages[0].pageEnabled = AMMU.Enable_YES; AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES; AMMU.configureAmmu = true; --------------------------------------
Cache.enableCache = true;
AMMU.largePages[0].translationEnabled = AMMU.Enable_YES;
AMMU.largePages[0].translatedAddress = 0x80000000;
AMMU.largePages[0].logicalAddress = 0x80000000;
AMMU.largePages[0].size = AMMU.Large_32M;
AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
AMMU.largePages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_CACHEABLE;
AMMU.largePages[0].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK;
AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
AMMU.largePages[1].translationEnabled = AMMU.Enable_YES;
AMMU.largePages[1].translatedAddress = 0x82000000;
AMMU.largePages[1].logicalAddress = 0x82000000;
AMMU.largePages[1].size = AMMU.Large_32M;
AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
AMMU.mediumPages[1].translatedAddress = 0x480C8000;
AMMU.mediumPages[1].logicalAddress = 0x480C8000;
AMMU.mediumPages[1].size = AMMU.Medium_256K;
With the settings above, I see that my program runs much faster, so I think that the cache is enabled.
1. I think that my settings above maps down to HW register CACHE_MMU_LARGE_ADDR_l, CACHE_MMU_LARGE_XLTE_l, CACHE_MMU_LARGE_POLY_l and CACHE_MMU_MED_ADDR_m, CACHE_MMU_MED_XLTE_m, CACHE_MMU_MED_POLY_m, But the AMMU contains so many more registers. Am I as a user responible for configuring them as well, or is SYS/BIOS doing that for me? If I'm responsible, where do I find documentation on how to do it?, the TRM contains no such information
2. I can't find in the TRM that the ducati M3 shared cache really consists of a L1 and L2 cache, is this true?
3. The TRM says (SPRUIG5, page 118 and 119), that only b28..31 can be set. This would mean that a 32MB page would have to be aligned on 256MB. I think that the TRM is wrong here. I think that a 32MB page only needs to be aligned on 32MB. My configuration above set seems to work and the second large page is aligned to 0x82000000, which is a 32MB alignment. Could you please comment on this?
4. When I link code to DDR1, i.e. 0xC0000000, the M3 stalls directly. If I link code to DDR0, i.e 0x80000000, it works fine. If I link data to DDR1, and have code in DDR0, it also works fine. Is there anything in the chip design that prevents the M3 from executing from DDR1?. I'm using a PG1.0 EVM board
BR
Niklas
