TDA4VH-Q1: SGMII MAC2MAC in linux

Tool/software:

Hi ti，

    Our hardware connection settings are as follows:

• CPSW9G Port8 SGMII   < - >  SJA1110 SGMII

    Based on this connection, we made the following changes in Linux:

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		//serial2 = &main_uart8;
		//serial2 = &main_uart2;
		serial2 = &main_uart3;
		mmc0 = &main_sdhci0;
		mmc1 = &main_sdhci1;
		i2c0 = &wkup_i2c0;
		i2c3 = &main_i2c0;
		//MCU-CPSW2G TX
		ethernet0 = &mcu_cpsw_port1;
		//MAIN-CPSW2G TX
		ethernet1 = &main_cpsw1_port1;
		//MAIN-CPSW9G T1
		//ethernet2 = &main_cpsw0_port3;
		ethernet2 = &main_cpsw0_port1;
		ethernet3 = &main_cpsw0_port2;
		ethernet4 = &main_cpsw0_port3;
		ethernet5 = &main_cpsw0_port4;
		ethernet6 = &main_cpsw0_port5;
		ethernet7 = &main_cpsw0_port6;
		ethernet8 = &main_cpsw0_port8;
	};

&serdes_ln_ctrl {
	idle-states = 
	//SoC_SERDESw_LANEx_IPa_LANEb
	//SERDES0
		<J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
		<J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_IP4_UNUSED>,
	//SERDES1
		<J784S4_SERDES1_LANE0_QSGMII_LANE3>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,
		<J784S4_SERDES1_LANE2_QSGMII_LANE1>, <J784S4_SERDES1_LANE3_QSGMII_LANE2>,
	//SERDES2
		<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
		<J784S4_SERDES2_LANE2_IP3_UNUSED>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>,
};

&serdes2 {
	status = "okay";
	serdes2_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};

	serdes2_sja1110_link: phy@3 {
		reg = <3>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz2 4>;
	};

};

&serdes_wiz2 {
	status = "okay";
};

&main_cpsw0_port8 {
	status = "okay";
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_sja1110_link>;
	phy-names = "mac", "serdes";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

    At the same time, we also modified the CPSW driver:

    We also dump the associated registers, as shown in the following figure:

    reg addr           reg val

    0x0c000810 : 0x00000021

    0x0c000814 :  0x0000003C

    0x0c000818 : 0x00009801

    0x0c000820 : 0x00001008

    As register description, the MAC on both sides do not link up. Can you help me see what's wrong?