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TDA4VM: Is there a fixed mapping relationship between serdes and CPSW9G port index?

Jay Sun
Expert 1095 points
Part Number: TDA4VM

Tool/software:

Hi

My current architecture is shown below. Is there a fixed mapping relationship between serdes and CPSW9G port index?

For example: serdes0_lane0 is mapped to CPSW9G port1. Or can all of this be configured via software? Is there a suggested mapping?

Best Regards,

Jay.

  • 0
    TI__Guru 63670 points

    Hi,

    Jay Sun said:
    My current architecture is shown below. Is there a fixed mapping relationship between serdes and CPSW9G port index?

    It is a fixed mapping, only few SerDes supports CPSW functionality.

    Please refer to below SerDes0, Serdes1 (2 Lanes SerDes) mapping of CPSW Ports.

    SerDes0, LN0: CPSW Port-1,
    SerDes0, LN1: CPSW Port-2,
    SerDes1, LN0: CPSW Port-3,
    SerDes1, LN1: CPSW Port-4,

    Also, refer to 4 Lane Serdes, has mapping of remaining 4 Ports of CPSW (Port-5, 6, 7 ,8) 



    TDA4VM has 5 SerDes supported, Four 2 Lane Serdes and One 4 Lane Serdes.

    Refer to TRM and Sysconfig tool for more details.

    Best Regards,
    Sudheer