8148 timer doc question

mes

Hi,

In SPRUGZ8, September 2011 Table 19-12, I think there is a mistake in the documentation for the Timer IRQEnable Set Register. I think some of the read/write definitions are mixed up. Can someone confirm this has already been found?

The rule above the table says:

Component interrupt request enable.
Write 1 to set (enable interrupt).
Readout equal to corresponding _CLR register.

Should be like this?

R0 Clear IRQ enable
W0 No action
R1 Clear IRQ enable
W1 IRQ event is enabled

or like this?

R0 No action
W0 Clear IRQ enable
R1 No action
W1 IRQ event is enabled

Should W0 clear the IRQ Enable and the reads simply be No Action????

Thanks,
Matt

Table 19-12. Timer IRQENABLE Set Register (IRQENABLE_SET) Field Descriptions
Bit Field Value Description

31-3 Reserved 0 Reserved

2 TCAR_EN_FLAG IRQ enable for Compare
R0 IRQ event is disabled
W0 No action
R1 IRQ event is enabled
W1 Clear IRQ enable

1 OVF_EN_FLAG IRQ enable for Overflow
R0 IRQ event is disabled
W0 No action
R1 IRQ event is enabled
W1 Clear IRQ enable

0 MAT_EN_FLAG IRQ enable for Match
R0 IRQ event is disabled
W0 No action
R1 IRQ event is enabled
W1 Clear IRQ enable

over 13 years ago

0 senthil.natarajan over 13 years ago

TI__Prodigy 180 points

Hi Matt,

I'm checking with the Timer experts on this and will follow up.

Thanks,

Senthil

0 Miguel A. Alanis over 13 years ago

TI__Genius 9490 points

Matt,

Sorry for the delay, looking into getting confirmation of the behavior of this register fields.

regards,

miguel

0 mes over 13 years ago in reply to Miguel A. Alanis

Intellectual 530 points

Through empirical means, I think the only problem is this part: W1 Clear IRQ enable

It just has to say Set and I think everything else is ok.

Ie, for match:

0 MAT_EN_FLAG IRQ enable for Match
R0 IRQ event is disabled
W0 No action
R1 IRQ event is enabled
W1 Set IRQ enable

I was initially confused by the format and the last item, but I think its correct this way, with the modification for W1.

Thanks,
Matt

0 Miguel A. Alanis over 13 years ago in reply to mes

TI__Genius 9490 points

Matt,

I am able to confim that you finding is correct and there is a documentation issue.

All three of the bits (MAT_EN_FLAG/OVF_EN_FLAG/TCAR_EN_FLAG) of this Timer IRQEnable Set Register currently have an incorrect description of the 'Write 1' function. As you stated it should read 'Write 1 : Set IRQ enable'.

thanks for the feedback and please excuse the delay.

miguel

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8148 timer doc question