Tool/software:
Hi Experts
We planned to use GPMC for bus connection between CPU and FPGA,
but some of the address lines conflict with some of the data lines of DSS (DisplaySubSystem),
and there was no function allocation on the other pins.
LCD control by CPU and device configuration using FPGA must be used.
We are considering the following policy, but are there any problems with its use?
・Conflicting pins (GPMC_A12 to A19, A26, and A27) are used as DSS and connected to the LCD.
・Non- conflicting pins (GPMC_A0 to A11, A20 to A25) are connected to FPGA.
・The FPGA address bus is used as an 18-bit bus with A0 to A11 and A20 to A25 side by side.
Or, a 28-bit bus from A0 to A27, but A12 to A19, A26, and A27 should be supported by GND connection,
etc., and an unusable area on the address map should be provided.
Best Regards,
Hidekazu