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Original question:

66AK2G12: Problem in high temperature operation

AM3352: How to set the TESTMODE register for USB

K.Z
Genius 3215 points

Part Number: AM3352

Tool/software:

Hi All,

We have received a query that there is a description of USB TESTMODE in the TRM of AM3352, but there is no register list.

My customer wants to run in TESTMODE, so please tell me how to set the registers.

Best Regards,

Ito

  • 0
    TI__Guru**** 233965 points

    Hello Ito

    Thank you for the query.

    Can you please check with the customer on the software development environment customer is using.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Genius 3215 points

    Hi Sreenivasa,

    Tnank you for your reply.

    The OS is ITRON-specification µC3.
    For details, please refer to the following website.
    μC3/Compact | eForce


    The integrated development environment is CCS.

    Best Regards,

    Ito

  • 0 in reply to K.Z
    TI__Guru**** 233965 points

    Hello Ito,

    Thank you.

    It is going to take some time to check if we could support.

    Regards,

    Sreenivasa

  • +1 in reply to K.Z
    TI__Guru**** 181966 points

    Hi Ito,

    We don't support other OS development, but here is the register information of TESTMODE.


    The testmode (8-bit) register address for USB0 is 0x4740140F, and for USB1 is 0x47401C0F.

    The information of the bits related to USB2.0 compliance test:

    bit 3 - Test_Packet: The CPU sets this bit to enter the Test_Packet test mode. In this mode, the USB controller repetitively transmits on the bus a 53-byte test packet. The test packet format is defined in the USB2.0 Specification, and must be loaded into the EP0 FIFO and TXPKTRDY bit has to be set in EP0 CSR register before the test mode is entered.

    bit 2 - Test_K: The CPU sets this bit to enter the Test_K test mode.

    bit 1 - Test_J: The CPU sets this bit to enter the Test_J test mode.

    bit 0 - Test_SE0_NAK: The CPU sets this bit to enter the Test_SE0_NAK test mode.