Other Parts Discussed in Thread: TMDS64EVM
Tool/software:
I am working with a customer trying to get their eMMC working with AM64x in U-Boot in MMC_HS_52 mode (High Speed 52MHz). They are experiencing some difficulty in this matter. They are working with Processor-SDK-Linux 9.00.00.03. We are aware that there have been a number of small but possibly important MMC changes between 9.00.00.03 and the latest 10.01.10.04 SDK version. We have in fact analyzed some of those differences, particularly the device tree differences in k3-am64-main.dtsi. While it may be a good idea to update to a newer SDK version, and the customer may do so anyways at some point, it is a bit more to take on than they wish at the moment. If possible, we need a near term solution on SDK version 9.00.00.03.
First off, we believe we have found a critical bug in am654_sdhci.c, which remains present in the latest 10.01.10.04 SDK. The "static const struct timing_data td[]" structure has an entry for MMC_HS with a typo. Instead of ti,itap-del-sel-mms-hs, we believe it should be ti,itap-del-sel-mmc-hs. This typo does not effect us, but it makes us wonder if all of the different modes in the table have indeed been testes.
The second thing we notice is that MMC_HS_52 mode is completely missing from the "td[]" table. Can this mode be supported by adding it to the table along with the necessary device tree entries?
In AM654_sdhci.c:
MMC_HS_52 = {"NULL, ti,itap-del-sel-mmc-hs52, MMC_CAP(MMC_HS_52)}
In device tree:
ti,itap-del-sel-mmc-hs52 = <0xa>
I believe the omission of an "otap" entry sets the OTAPDLYEN to 0. Please confirm.
Values taken from the following table:
Something else that is a bit confusing is the the correct value for the HIGH_SPEED_ENA field found in the MMCSD0_HOST_CONTROL1 register. With this bit clear, the signal timing to match Figure 6-61 below. If this bit is set high, then the data starts transitioning at the positive edge of the clock.
Here is an excerpt out of the TRM:
Which seems to contradict the expected Figure 6-61 timing diagram from the datasheet by recommending it to be set in MMC_HS_52 mode, thus moving the data transition to the positive clock edge. What is the correct setting of this bit in MMC_HS_52 mode? U-boot seems to be following the TRM interpretation.
If using MMC_HS_52, which I think complies with Table 6-73 (if you ignore the 52 and treat it as 50; 50 MHz is what is seen on the scope), then u-boot sets the HIGH_SPEED_ENA bit. This causes a positive edge launch and breaks timing (at least with the OTAPDLYENA = 0 that the datasheet recommends).
Lastly, the customer does appear to have gotten MMC_DDR_52 mode to work. Validation is ongoing. They may end up just using the MMC_DDR_52 mode. However, they do not require the added bandwidth, and were planning to stick to MMC_HS_52 mode for added design margin.
Thanks,
Stuart