TDA4VE-Q1: CSIRX image fragmentation issue

Part Number: TDA4VE-Q1

Tool/software:

Hi expert,

Our customer find serious image fragmentation issue on TDA4VE as the below video shown. Could you please help check how to debug?

SDK:

ti-processor-sdk-rtos-j721s2-evm-08_06_01_03

Camera:

4*1920*1536@25fps

Issue describtion:

1. 4 cameras connected to CSI-RX and TDA4VE output the video to cookpit thru ethernet. We can find serious image fragmentation in about 5 secs.

2. We find capture statistic, CRC/ECC/OVERFLOW keeps 0 in MCU2_0, but frame drop count keeps increasing;

3. DDR statistic as below:

Test and Result:

1. If only 1 camera is connected, there is no issue;

2. We try to increase the buffer of capture node from 4 to 6; frame drop count almost disappear, and there is some improvement to this issue, but cannot totally fix it;

capture statistic as below:

3.  If we disable BEV fastray and infopost in C7, there will be no issue;

4. We try to modify the CSIRX driver config as below, and reproduce probability is decreased from 5s/1time to 1minute/1time;

file

function

change

pdk_j721s2_08_06_01_03/packages/ti/drv/csirx/csirx.h

increase chCfgPrms->rxChParams.addrType = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_NON_COHERENT;

chCfgPrms->rxChParams.busOrderId  = 12U;

5. We try to follow suggestions in below E2E link to modify CSIRX driver. But the error is reported.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1308436/tda4vm-8m-camera-run-report-incomplete-frame-error/4989762?tisearch=e2e-quicksearch&keymatch=UDMA_CH_TYPE_RX_UHC#4989762

file

function

change

packages/ti/drv/csirx/csirx.h

Csirx_chCfgInit

add "chCfgPrms->rxChParams.addrType = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_NON_COHERENT;" line at the end of the function.

Change  below statement

        UdmaChRxPrms_init(&chCfgPrms->rxChParams, UDMA_CH_TYPE_RX);

     to

        UdmaChRxPrms_init(&chCfgPrms->rxChParams, UDMA_CH_TYPE_RX_UHC);

packages/ti/drv/udma/src/udma_ch.c

UdmaChUtcPrms_init

change below statement

           utcPrms->addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS;

  to 

          utcPrms->addrType       = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_NON_COHERENT;

//TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS;

packages/ti/drv/csirx/src/csirx_drvUdma.c

CsirxDrv_setChUdmaParams

change below statement 

                chType = UDMA_CH_TYPE_RX;

 to

                chType = UDMA_CH_TYPE_RX_UHC;

After above modification, capture node report below error when MCU2_0 start up. 

About the issue that UDMA_CH_TYPE_RX_HC and UDMA_CH_TYPE_RX_UHC channel allocation fail, customer look into Udma_rmAllocRxHcCh() and Udma_rmAllocRxUhcCh() and find that numRxHcCh and numRxUhcCh are 0.

Customer traced the code and found that it uses Udma_rmGetSciclientDefaultBoardCfgRmRange() to Query all the resource ranges from the Sciclient Default BoardCfg. if customer wants to use RX hc and uhc channel, what config need to do?

Best Regards,

Xingyu Zhu

  • Hi Xingyu,

    In SDK08.06 release, there was no support for QoS setting on TDA4AE/VE devices. So can you please apply the attached settings from below link and try it again? Also please keep the order id to be 12 in the CSIRX.h header file. 

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1214683/faq-processor-sdk-j721s2-how-to-enable-qos-for-dss-in-sbl-or-in-spl-boot-flow

    Regards,

    Brijesh

  • Hi Brijesh,

    Thanks for your reply. Our customer has integrated this QoS patch at the beginning. They also have tried to enable more QoS, but both no improvement.

     In pdk_j721s2_08_06_01_03/packages/ti/drv/csirx/csirx.h

    Change (chCfgPrms->rxChParams.busOrderId  = 12U,  chCfgPrms->rxChParams.addrType = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_NON_COHERENT;)

    static void J721S2_SetupQoS()

    {

        setup_navss_nb();

        /* Workaround to unblock PDK-8359 .

         * setup_main_r5f_qos() results in crashing the UDMA DRU examples on

         * mcu2_0(with SBL uart boot mode) during CSL_REG64_WR(&pRegs->DRUQueues.CFG[queueId], regVal);

         * Hence commenting out the following. */

        setup_main_r5f_qos();

        setup_mcu_r5f_qos();

        setup_vpac_qos();

        setup_dmpac_qos();

        setup_dss_qos();

        /* setup_gpu_qos(); */

        setup_encoder_qos();

    }

    Could you please help to check the possible reason? And do you have any suggestions for test item5? Thanks

  • Hi Xingyu,

    Can we please readback 0x03702010 and 0x03703010 and confirm that value are set to 0x2 and 0x4 respectively? 

    Most likely, CSIRX is detecting the short/long frame error. In order to confirm it, can we please add below code in ti-processor-sdk-rtos-j721s2-evm-08_06_00_11/tiovx/kernels_j7/hwa/capture/vx_capture_target.c file, in tivxCaptureDequeueFrameFromDriver API.

    chId = tivxCaptureGetNodeChannelNum(
    prms,
    instIdx,
    fvid2Frame->chNum);

    if (FVID2_FRAME_STATUS_COMPLETED != fvid2Frame->status)
    {
        VX_PRINT(VX_ZONE_ERROR,
            " CAPTURE: ERROR: Short/Long Frame Detected for ChId%d!!!\n", chId);
    }

    It essentially means CSIRX is not able to write fast enough. Can you try changing busOrderId in the CSIRX driver to value 15? 

    chCfgPrms->rxChParams.busOrderId  = 15U

    Regards,

    Brijesh

  • Hi Brijesh,

    Can we please readback 0x03702010 and 0x03703010 and confirm that value are set to 0x2 and 0x4 respectively? 

    root@imotion:/mnt# ./devmem2 0x03702010
    /dev/mem opened.
    Memory mapped at address 0xffff83573000.
    Read at address 0x03702010 (0xffff83573010): 0x00000002
    root@imotion:/mnt# ./devmem2 0x03703010
    /dev/mem opened.
    Memory mapped at address 0xffff8c1c7000.
    Read at address 0x03703010 (0xffff8c1c7010): 0x00000004

    In order to confirm it, can we please add below code

    Below is the log.

    [MCU2_0] 25.340497 s: VX_ZONE_ERROR:[tivxCaptureDequeueFrameFromDriver:889] CAPTURE: ERROR: Short/Long Frame Detected for ChId0!!!
    [MCU2_0] 25.340577 s: VX_ZONE_ERROR:[tivxCaptureDequeueFrameFromDriver:889] CAPTURE: ERROR: Short/Long Frame Detected for ChId1!!!
    [MCU2_0] 25.340640 s: VX_ZONE_ERROR:[tivxCaptureDequeueFrameFromDriver:889] CAPTURE: ERROR: Short/Long Frame Detected for ChId2!!!
    [MCU2_0] 25.340700 s: VX_ZONE_ERROR:[tivxCaptureDequeueFrameFromDriver:889] CAPTURE: ERROR: Short/Long Frame Detected for ChId3!!!
    [MCU2_0] 28.036739 s: VX_ZONE_ERROR:[tivxCaptureDequeueFrameFromDriver:889] CAPTURE: ERROR: Short/Long Frame Detected for ChId0!!!
    [MCU2_0] 28.036853 s: VX_ZONE_ERROR:[tivxCaptureDequeueFrameFromDriver:889] CAPTURE: ERROR: Short/Long Frame Detected for ChId1!!!
    [MCU2_0] 28.036919 s: VX_ZONE_ERROR:[tivxCaptureDequeueFrameFromDriver:889] CAPTURE: ERROR: Short/Long Frame Detected for ChId2!!!
    [MCU2_0] 28.036991 s: VX_ZONE_ERROR:[tivxCaptureDequeueFrameFromDriver:889] CAPTURE: ERROR: Short/Long Frame Detected for ChId3!!!

    Can you try changing busOrderId in the CSIRX driver to value 15? 

    Customer has tried different RX and TX busOrderId combination and the test result is as below:

    RX ID TX ID issue frequency
    15 8 1times/min
    12 8 1times/min
    12 12 6times/min
    8 8 30times/min
    8 12  30times/min
  • It essentially means CSIRX is not able to write fast enough

    Customer find we can adjust burstsize in pdk_j721s2_08_06_01_03/packages/ti/drv/udma/src/udma_ch.c UdmaChRxPrms_init(), but need to enable HC or UHC channel first.

    Customer try to add some print in the UDMA driver in Kernel and find HC and UHC channel is not 0. But when they try to config CSIRX channel to UDMA_CH_FLAG_HC or UDMA_CH_FLAG_UHC, Udma_rmAllocRxHcCh() will be allocated fail since numRxHcCh. You can find the detail in test item5.

    So does it mean we need to enable CSIRX UDMA UHC channel first?

  • Hi Xingyu,

    CSIRX internally uses BCDMA channels, so i really doubt it can use HC/UHC channels of the UDMA. 

    Since you are using Short/Long frame errors from the CSIRX, it means CSIRX is not able to write the data fast enough and so you are seeing artifacts on the display. 

    I dont understand on TX ID in the above table. Which parameter are you changing here? 

    Essentially we should just need to change rxChPrms.busOrderId to value more than 10. This should help. 

    What all other components are running in the system? Is it possible to reproduce this issue on EVM?

    Regards,

    Brijesh

  • Hi Brijesh,

    Thanks for your reply.

    CSIRX internally uses BCDMA channels, so i really doubt it can use HC/UHC channels of the UDMA. 

    BCDMA has 16 normal channels, so it seems HC/UHC cannot be used;

    I dont understand on TX ID in the above table. Which parameter are you changing here? 

    Customer try to modify TX ID in pdk_j721s2_08_06_01_03/packages/ti/drv/csitx/src/csitx_drvInit.c Csitx_chCfgInit() chCfgPrms->txChParams.busOrderId

    What all other components are running in the system?

    Customer is running some ADAS-related function. The running applications include

    1. Capture, LDC/MSC

    2. An NV12-to-tensor operator running on C7x_2

    3. BEV processing divided into three stages, distributed across C7x_1 and C7x_2.

    Is it possible to reproduce this issue on EVM?

    Customer has checked this. It is very hard to port their own application to EVM. 

  • Besides, in the CSIRx driver, after enabling CSIRX_DRV_ENABLE_DEBUG, customer observed a phenomenon while reproducing Short/Long Frame errors. When an error frame occurs, the timestamp difference between the current error frame and the previous frame is not the expected 40ms (camera frame rate is 25fps). What could be the possible reason?

    As shown in the figure below, frame status 0x1 indicates FVID2_FRAME_STATUS_COMPLETED, and frame status 0x4 indicates FVID2_FRAME_STATUS_ERROR. The timestamps (TS) for four consecutive frames are 61659, 61699, 61729, and 61779. The timestamp difference for the error frame is 61729 - 61699 = 30ms, which is less than the expected 40ms.

    Below is the log.

    mcu20_csirx_debug.txt

  • Hi Xingyu,

    Its surprising that you are getting error frames within 30ms. That shouldn't have happened. 

    But the main issue is, we shouldn't have seen these errors. 

    There is a parameter in the CSIRX node to use multiple pixels at a time, can you please try changing it? Can you set numPixels in tivx_capture_inst_params_t structure to value 1 and see if it helps?

    I am also reviewing other changes and see if there is any more change required. 

    Regards,

    Brijesh

  • Hi Brijesh,

    Thanks for your reply. Customer has tried changing the parameter and tested twice. No obvious improvement can be found and the error frame still exist.

    1. vision_apps/modules/src/app_capture_module.c configure_capture_params() add captureObj->params.instCfg[id].numPixels = 1U;
    2. pdk_j721s2_08_06_01_03/packages/ti/drv/csirx/csirx.h Csirx_instCfgInit()
    change
    modCfgPrms->numPixelsStrm0 = (uint32_t)0U;
    to
    modCfgPrms->numPixelsStrm0 = (uint32_t)1U;

  • Hi Xingyu,

    ok, frame drop is not an issue, but the main issue is, it is reporting short/long frame errors. 

    I want to make one more change in the CSIRX driver and see if it helps. I will share the changes tomorrow. 

    Could you please confirm that OCM memory in MCU domain is available for CSIRX to use? I mean are you using SBL or BootApp? They both use OCM memory. 

    Regards,

    Brijesh

  • Hi Brijesh.,

    I mean are you using SBL or BootApp

    Customer is using SBL;

    Could you please confirm that OCM memory in MCU domain is available for CSIRX to use?

    Customer OCM usage is as below:

  • Hi Xingyu,

    Do they also use Main Domain OCM memory?

    Regards,

    Brijesh 

  • Hi Brijesh,

    Do they also use Main Domain OCM memory?

    We are not very sure. Customer checked the system_memory_map and listed all the items related with OCMRAM and OCRAM.

  • Hi Xingyu,

    I asked because i see sections allocated in OCM memory like "Vector" "Common" and "NoCache", so wondering if Main Domain OCM memory is also used.

    I am assuming that that it is not and will use it to store some internal data of CSIRX driver.

    Can you also pleas confirm that customer is using only CSIRX instance0 and they are using it for capturing 4 channel/camera data? Because this memory is small, it may not be sufficient to fit complete data for all instances and channels.

    Regards,

    Brijesh

  • Hi Brijesh,

    Can you also pleas confirm that customer is using only CSIRX instance0 and they are using it for capturing 4 channel/camera data?

    Yes, customer is using CSIRX0 for capturing 4 camera data (1920x1536). 

  • Thanks Xingyu, i will share you the changes in CSIRX driver on SDK08.06 to try it out in a day or two. 

    Regards,

    Brijesh

  • Hi Xingyu,

    Can you please attached patches on PDK drivers and Vision apps and re-run the usecase with the changes? These changes moves the CSIRX descriptors to internal memory. Lets see if this change helps in fixing this issue. 

    /cfs-file/__key/communityserver-discussions-components-files/791/PDK_5F00_Moved_5F00_CSIRX_5F00_Desc_5F00_To_5F00_Internal_5F00_Mem.patch

    /cfs-file/__key/communityserver-discussions-components-files/791/Vision_5F00_Apps_5F00_Moved_5F00_CSIRX_5F00_Desc_5F00_To_5F00_Internal_5F00_Mem.patch

    Regards,

    Brijesh

  • Hi Brijesh,

    Thanks for your reply.

    Following the patch provided, after moving the csirx desc related data to OCRAM, testing revealed that image-related initialization and streaming are not working correctly. Customer collected information:
    1. The execution result of app_status_monitor.out. There is no output after applying the OCRAM patch;

    app_status_monitor_output_csirx_desc.txt
    root@imotion:/mnt# ./app_status_monitor.out
    APP: Init ... !!!
    MEM: Init ... !!!
    MEM: Initialized DMA HEAP (fd=4) !!!
    MEM: Init ... Done !!!
    IPC: Init ... !!!
    file_deref_link: readlink failed for /sys/bus/platform/devices/5d00000.r5f
    _rpmsg_char_find_rproc: 5d00000.r5f device is mostly yet to be created!
    IPC: ERROR: Unable to create TX channels for CPU [mcu2_1] !!!
    IPC: Init ... Done !!!
    APP: ERROR: IPC init failed !!!
    REMOTE_SERVICE: Init ... !!!
    file_deref_link: readlink failed for /sys/bus/platform/devices/5d00000.r5f
    _rpmsg_char_find_rproc: 5d00000.r5f device is mostly yet to be created!
    REMOTE_SERVICE: Init ... Done !!!
       175.924890 s: GTC Frequency = 200 MHz
    APP: Init ... Done !!!
       175.926890 s:  VX_ZONE_INIT:Enabled
       175.927205 s:  VX_ZONE_ERROR:Enabled
       175.927313 s:  VX_ZONE_WARNING:Enabled
       175.929682 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
       175.930066 s:  VX_ZONE_INIT:[tivxHostInitLocal:93] Initialization Done for HOST !!!
    
    Summary of CPU load,
    ====================
    
    CPU: mpu1_0: TOTAL LOAD =   0. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
    
    
    

    app_status_monitor_output_original.txt
    root@imotion:/mnt# ./app_status_monitor.out
    APP: Init ... !!!
    MEM: Init ... !!!
    MEM: Initialized DMA HEAP (fd=4) !!!
    MEM: Init ... Done !!!
    IPC: Init ... !!!
    file_deref_link: readlink failed for /sys/bus/platform/devices/5d00000.r5f
    _rpmsg_char_find_rproc: 5d00000.r5f device is mostly yet to be created!
    IPC: ERROR: Unable to create TX channels for CPU [mcu2_1] !!!
    IPC: Init ... Done !!!
    APP: ERROR: IPC init failed !!!
    REMOTE_SERVICE: Init ... !!!
    file_deref_link: readlink failed for /sys/bus/platform/devices/5d00000.r5f
    _rpmsg_char_find_rproc: 5d00000.r5f device is mostly yet to be created!
    REMOTE_SERVICE: Init ... Done !!!
       999.502212 s: GTC Frequency = 200 MHz
    APP: Init ... Done !!!
       999.503999 s:  VX_ZONE_INIT:Enabled
       999.504046 s:  VX_ZONE_ERROR:Enabled
       999.504053 s:  VX_ZONE_WARNING:Enabled
       999.505321 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
       999.506753 s:  VX_ZONE_INIT:[tivxHostInitLocal:93] Initialization Done for HOST !!!
    
    Summary of CPU load,
    ====================
    
    CPU: mpu1_0: TOTAL LOAD = 100. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
    CPU: mcu2_0: TOTAL LOAD =  12. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
    REMOTE_SERVICE: TX: FAILED: mpu1_0 -> mcu2_1 (port 21) cmd = 0x00000002, prm_size = 12 bytes
    CPU:  c7x_1: TOTAL LOAD =  21. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
    CPU:  c7x_2: TOTAL LOAD =  69. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
    
    
    HWA performance statistics,
    ===========================
    
    HWA:   LDC : LOAD =  37.45 % ( 259 MP/s )
    HWA:   MSC0: LOAD =  57.56 % ( 388 MP/s )
    REMOTE_SERVICE: TX: FAILED: mpu1_0 -> mcu2_1 (port 21) cmd = 0x00000006, prm_size = 256 bytes
    
    
    DDR performance statistics,
    ===========================
    
    REMOTE_SERVICE: TX: FAILED: mpu1_0 -> mcu2_1 (port 21) cmd = 0x00000007, prm_size = 36 bytes
    
    
    Detailed CPU performance/memory statistics,
    ===========================================
    
    DDR_SHARED_MEM: Alloc's: 0 alloc's of 0 bytes
    DDR_SHARED_MEM: Free's : 0 free's  of 0 bytes
    DDR_SHARED_MEM: Open's : 0 allocs  of 0 bytes
    DDR_SHARED_MEM: Total size: 536870912 bytes
    
    CPU: mcu2_0: TASK:           IPC_RX:   0.29 %
    CPU: mcu2_0: TASK:       REMOTE_SRV:   0.15 %
    CPU: mcu2_0: TASK:        LOAD_TEST:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_CPU_0:   0. 0 %
    CPU: mcu2_0: TASK:        TIVX_V1NF:   0. 0 %
    CPU: mcu2_0: TASK:      TIVX_V1LDC1:   2.93 %
    CPU: mcu2_0: TASK:       TIVX_V1SC1:   4.77 %
    CPU: mcu2_0: TASK:      TIVX_V1MSC2:   0. 0 %
    CPU: mcu2_0: TASK:       TIVXVVISS1:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_CAPT1:   1. 6 %
    CPU: mcu2_0: TASK:       TIVX_CAPT2:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_DISP1:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_DISP2:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_CSITX:   0.97 %
    CPU: mcu2_0: TASK:       TIVX_CAPT3:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_CAPT4:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_CAPT5:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_CAPT6:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_CAPT7:   0. 0 %
    CPU: mcu2_0: TASK:       TIVX_CAPT8:   0. 0 %
    CPU: mcu2_0: TASK:      TIVX_DPM2M1:   1.63 %
    CPU: mcu2_0: TASK:      TIVX_DPM2M2:   0. 0 %
    CPU: mcu2_0: TASK:      TIVX_DPM2M3:   0. 0 %
    CPU: mcu2_0: TASK:      TIVX_DPM2M4:   0. 0 %
    
    CPU: mcu2_0: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   16707328 B ( 99 % unused)
    CPU: mcu2_0: HEAP:           L3_MEM: size =     524288 B, free =     524032 B ( 99 % unused)
    
    REMOTE_SERVICE: TX: FAILED: mpu1_0 -> mcu2_1 (port 21) cmd = 0x00000003, prm_size = 388 bytes
    CPU:  c7x_1: TASK:           IPC_RX:   0. 5 %
    CPU:  c7x_1: TASK:       REMOTE_SRV:   0. 0 %
    CPU:  c7x_1: TASK:        LOAD_TEST:   0. 0 %
    CPU:  c7x_1: TASK:      TIVX_C71_P1:  20.12 %
    CPU:  c7x_1: TASK:      TIVX_C71_P2:   0. 0 %
    CPU:  c7x_1: TASK:      TIVX_C71_P3:   0. 0 %
    CPU:  c7x_1: TASK:      TIVX_C71_P4:   0. 0 %
    CPU:  c7x_1: TASK:      TIVX_C71_P5:   0. 0 %
    CPU:  c7x_1: TASK:      TIVX_C71_P6:   0. 0 %
    CPU:  c7x_1: TASK:      TIVX_C71_P7:   0. 0 %
    CPU:  c7x_1: TASK:      TIVX_C71_P8:   0. 0 %
    CPU:  c7x_1: TASK:      IPC_TEST_RX:   0. 0 %
    CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
    CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
    CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
    
    CPU:  c7x_1: HEAP:    DDR_LOCAL_MEM: size =  268435456 B, free =  229828096 B ( 85 % unused)
    CPU:  c7x_1: HEAP:           L3_MEM: size =    1572864 B, free =    1048576 B ( 66 % unused)
    CPU:  c7x_1: HEAP:           L2_MEM: size =     458752 B, free =          0 B (  0 % unused)
    CPU:  c7x_1: HEAP:           L1_MEM: size =      16384 B, free =          0 B (  0 % unused)
    CPU:  c7x_1: HEAP:  DDR_SCRATCH_MEM: size =  385875968 B, free =  385335040 B ( 99 % unused)
    
    CPU:  c7x_2: TASK:           IPC_RX:   0. 6 %
    CPU:  c7x_2: TASK:       REMOTE_SRV:   0. 0 %
    CPU:  c7x_2: TASK:        LOAD_TEST:   0. 0 %
    CPU:  c7x_2: TASK:         TIVX_CPU:  67.96 %
    CPU:  c7x_2: TASK:      IPC_TEST_RX:   0. 0 %
    CPU:  c7x_2: TASK:      IPC_TEST_TX:   0. 0 %
    CPU:  c7x_2: TASK:      IPC_TEST_TX:   0. 0 %
    CPU:  c7x_2: TASK:      IPC_TEST_TX:   0. 0 %
    
    CPU:  c7x_2: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   16615424 B ( 99 % unused)
    CPU:  c7x_2: HEAP:           L2_MEM: size =     458752 B, free =          0 B (  0 % unused)
    CPU:  c7x_2: HEAP:           L1_MEM: size =      16384 B, free =      16384 B (100 % unused)
    CPU:  c7x_2: HEAP:  DDR_SCRATCH_MEM: size =   67108864 B, free =   64922624 B ( 96 % unused)
    
    
    REMOTE_SERVICE: TX: FAILED: mpu1_0 -> mcu2_1 (port 21) cmd = 0x00000001, prm_size = 0 bytes
    REMOTE_SERVICE: TX: FAILED: mpu1_0 -> mcu2_1 (port 21) cmd = 0x00000005, prm_size = 0 bytes
    REMOTE_SERVICE: TX: FAILED: mpu1_0 -> mcu2_1 (port 21) cmd = 0x00000008, prm_size = 0 bytes
    
    

    2. The mcu20 bootlog. After applying the OCRAM patch, the app gets stuck in the function ownGraphNodeKernelInit() during the execution of vxVerifyGraph() in tiovx/source/framework/vx_graph_verify.c, which prevents the camera’s initialization and streaming from proceeding;

    mcu20_bootlog_csirx_desc.txt
    [MCU2_0]      2.063281 s: CIO: Init ... Done !!!
    [MCU2_0]      2.063338 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_0]      2.063372 s: CPU is running FreeRTOS
    [MCU2_0]      2.063393 s: APP: Init ... !!!
    [MCU2_0]      2.063412 s: SCICLIENT: Init ... !!!
    [MCU2_0]      2.063602 s: SCICLIENT: DMSC FW version [8.6.3--1-g2249f (Chill Capybara]
    [MCU2_0]      2.063636 s: SCICLIENT: DMSC FW revision 0x8
    [MCU2_0]      2.063663 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_0]      2.063693 s: SCICLIENT: Init ... Done !!!
    [MCU2_0]      2.063716 s: UDMA: Init ... !!!
    [MCU2_0]      2.066253 s: UDMA: Init ... Done !!!
    [MCU2_0]      2.066296 s: UDMA: Init ... !!!
    [MCU2_0]      2.067729 s: UDMA: Init for CSITX/CSIRX ... Done !!!
    [MCU2_0]      2.067786 s: MEM: Init ... !!!
    [MCU2_0]      2.067828 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!!
    [MCU2_0]      2.067890 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
    [MCU2_0]      2.067941 s: MEM: Init ... Done !!!
    [MCU2_0]      2.067962 s: IPC: Init ... !!!
    [MCU2_0]      2.068008 s: IPC: 4 CPUs participating in IPC !!!
    [MCU2_0]      2.068044 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_0]      2.068072 s: IPC: HLOS is ready !!!
    [MCU2_0]      2.076071 s: IPC: Init ... Done !!!
    [MCU2_0]      2.076115 s: APP: Syncing with 3 CPUs ... !!!
    [MCU2_0]      2.076150 s: APP: Syncing with 3 CPUs ... Done !!!
    [MCU2_0]      2.076180 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_0]      2.077432 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_0]      2.077473 s: FVID2: Init ... !!!
    [MCU2_0]      2.077577 s: FVID2: Init ... Done !!!
    [MCU2_0]      2.077609 s: DSS: Init ... !!!
    [MCU2_0]      2.077631 s: DSS: Display type is eDP !!!
    [MCU2_0]      2.077655 s: DSS: M2M Path is enabled !!!
    [MCU2_0]      2.077677 s: DSS: SoC init ... !!!
    [MCU2_0]      2.077697 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
    [MCU2_0]      2.077912 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.077940 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2
    [MCU2_0]      2.078162 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.078187 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2
    [MCU2_0]      2.078437 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.078467 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2
    [MCU2_0]      2.078614 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.078639 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2
    [MCU2_0]      2.078728 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.078787 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
    [MCU2_0]      2.078879 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.078906 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=158 clk=3 freq=253044000
    [MCU2_0]      2.079891 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
    [MCU2_0]      2.079917 s: SCICLIENT: Sciclient_pmModuleClkRequest module=158 clk=3 state=2 flag=2
    [MCU2_0]      2.080682 s: SCICLIENT: Sciclient_pmModuleClkRequest success
    [MCU2_0]      2.080708 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=2
    [MCU2_0]      2.081050 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.081075 s: DSS: SoC init ... Done !!!
    [MCU2_0]      2.081097 s: DSS: Board init ... !!!
    [MCU2_0]      2.081117 s: DSS: Board init ... Done !!!
    [MCU2_0]      2.103611 s: DSS: Display is not connected
    [MCU2_0]      2.103660 s: DSS: Init ... Done !!!
    [MCU2_0]      2.103684 s: VHWA: VPAC Init ... !!!
    [MCU2_0]      2.103706 s: SCICLIENT: Sciclient_pmSetModuleState module=361 state=2
    [MCU2_0]      2.103939 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.103969 s: VHWA: LDC Init ... !!!
    [MCU2_0]      2.108501 s: VHWA: LDC Init ... Done !!!
    [MCU2_0]      2.108543 s: VHWA: MSC Init ... !!!
    [MCU2_0]      2.121243 s: VHWA: MSC Init ... Done !!!
    [MCU2_0]      2.121278 s: VHWA: NF Init ... !!!
    [MCU2_0]      2.122380 s: VHWA: NF Init ... Done !!!
    [MCU2_0]      2.122413 s: VHWA: VISS Init ... !!!
    [MCU2_0]      2.135450 s: VHWA: VISS Init ... Done !!!
    [MCU2_0]      2.135494 s: VHWA: VPAC Init ... Done !!!
    [MCU2_0]      2.135530 s:  VX_ZONE_INIT:Enabled
    [MCU2_0]      2.135554 s:  VX_ZONE_ERROR:Enabled
    [MCU2_0]      2.135576 s:  VX_ZONE_WARNING:Enabled
    [MCU2_0]      2.136624 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0
    [MCU2_0]      2.136812 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF
    [MCU2_0]      2.136993 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1
    [MCU2_0]      2.137171 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1
    [MCU2_0]      2.137342 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2
    [MCU2_0]      2.137577 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1
    [MCU2_0]      2.137767 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1
    [MCU2_0]      2.137955 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2
    [MCU2_0]      2.138151 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1
    [MCU2_0]      2.138343 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2
    [MCU2_0]      2.138517 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX
    [MCU2_0]      2.138702 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3
    [MCU2_0]      2.138901 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4
    [MCU2_0]      2.139096 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5
    [MCU2_0]      2.139284 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6
    [MCU2_0]      2.139478 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7
    [MCU2_0]      2.139670 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8
    [MCU2_0]      2.139861 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1
    [MCU2_0]      2.140042 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2
    [MCU2_0]      2.140221 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3
    [MCU2_0]      2.140403 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4
    [MCU2_0]      2.140575 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX2
    [MCU2_0]      2.140616 s:  VX_ZONE_INIT:[tivxInitLocal:131] Initialization Done !!!
    [MCU2_0]      2.140645 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_0]      2.167299 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_0]      2.167336 s: CSI2RX: Init ... !!!
    [MCU2_0]      2.167358 s: SCICLIENT: Sciclient_pmSetModuleState module=136 state=2
    [MCU2_0]      2.167514 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.167542 s: SCICLIENT: Sciclient_pmSetModuleState module=38 state=2
    [MCU2_0]      2.167697 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.167722 s: SCICLIENT: Sciclient_pmSetModuleState module=39 state=2
    [MCU2_0]      2.167846 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.167873 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
    [MCU2_0]      2.167973 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.167999 s: SCICLIENT: Sciclient_pmSetModuleState module=153 state=2
    [MCU2_0]      2.168095 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.168257 s: CSI2RX: Init ... Done !!!
    [MCU2_0]      2.168283 s: CSI2TX: Init ... !!!
    [MCU2_0]      2.168303 s: SCICLIENT: Sciclient_pmSetModuleState module=136 state=2
    [MCU2_0]      2.168415 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.168442 s: SCICLIENT: Sciclient_pmSetModuleState module=40 state=2
    [MCU2_0]      2.168565 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.168590 s: SCICLIENT: Sciclient_pmSetModuleState module=41 state=2
    [MCU2_0]      2.168705 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.168730 s: SCICLIENT: Sciclient_pmSetModuleState module=363 state=2
    [MCU2_0]      2.168839 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.168904 s: CSI2TX: Init ... Done !!!
    [MCU2_0]      2.168929 s: ISS: Init ... !!!
    [MCU2_0]      2.168964 s: IssSensor_bl031_Init successful!
    [MCU2_0]      2.168987 s: IssSensor_Init ... Done !!!
    [MCU2_0]      2.169044 s: IttRemoteServer_Init ... Done !!!
    [MCU2_0]      2.169069 s: VISS REMOTE SERVICE: Init ... !!!
    [MCU2_0]      2.169120 s: VISS REMOTE SERVICE: Init ... Done !!!
    [MCU2_0]      2.169145 s: UDMA Copy: Init ... !!!
    [MCU2_0]      2.171262 s: UDMA Copy: Init ... Done !!!
    [MCU2_0]      2.171336 s: APP: Init ... Done !!!
    [MCU2_0]      2.171377 s: SCICLIENT: Sciclient_pmSetModuleState module=219 state=2
    [MCU2_0]      2.171527 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.171554 s: SCICLIENT: Sciclient_pmSetModuleState module=215 state=2
    [MCU2_0]      2.171670 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.171710 s: APP: Run ... !!!
    [MCU2_0]      2.171730 s: IPC: Starting echo test ...
    [MCU2_0]      2.173417 s: APP: Run ... Done !!!
    [MCU2_0]      2.173492 s: write 9539 start..........
    [MCU2_0]      2.173661 s: 9539 regAddr[0] = 0xfc status = 0
    [MCU2_0]      2.173832 s: 9539 regAddr[1] = 0xf0 status = 0
    [MCU2_0]      2.173953 s: write 9539 regAddr[6] = 0x0 status = 0
    [MCU2_0]      2.174070 s: write 9539 regAddr[7] = 0xf0 status = 0
    [MCU2_0]      2.174685 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] C7X_1[P] C7X_2[.]
    [MCU2_0]      2.174753 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] C7X_1[P] C7X_2[P]
    [MCU2_0]     12.656107 s:  i2cins: 0x1, addr: 0x6b
    [MCU2_0]     12.656373 s:  DeserializerInit successful

    mcu20_bootlog_original.txt
    source ./vision_apps_init.sh
    root@imotion:/opt/vision_apps# [MCU2_0]      2.553547 s: CIO: Init ... Done !!!
    [MCU2_0]      2.553607 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_0]      2.553640 s: CPU is running FreeRTOS
    [MCU2_0]      2.553661 s: APP: Init ... !!!
    [MCU2_0]      2.553680 s: SCICLIENT: Init ... !!!
    [MCU2_0]      2.553859 s: SCICLIENT: DMSC FW version [8.6.3--1-g2249f (Chill Capybara]
    [MCU2_0]      2.553894 s: SCICLIENT: DMSC FW revision 0x8
    [MCU2_0]      2.553923 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_0]      2.553953 s: SCICLIENT: Init ... Done !!!
    [MCU2_0]      2.553976 s: UDMA: Init ... !!!
    [MCU2_0]      2.555263 s: UDMA: Init ... Done !!!
    [MCU2_0]      2.555303 s: UDMA: Init ... !!!
    [MCU2_0]      2.558068 s: UDMA: Init for CSITX/CSIRX ... Done !!!
    [MCU2_0]      2.558128 s: MEM: Init ... !!!
    [MCU2_0]      2.558161 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!!
    [MCU2_0]      2.558221 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 524288 bytes !!!
    [MCU2_0]      2.558273 s: MEM: Init ... Done !!!
    [MCU2_0]      2.558295 s: IPC: Init ... !!!
    [MCU2_0]      2.558342 s: IPC: 4 CPUs participating in IPC !!!
    [MCU2_0]      2.558379 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_0]      2.558409 s: IPC: HLOS is ready !!!
    [MCU2_0]      2.566923 s: IPC: Init ... Done !!!
    [MCU2_0]      2.566969 s: APP: Syncing with 3 CPUs ... !!!
    [MCU2_0]      2.567003 s: APP: Syncing with 3 CPUs ... Done !!!
    [MCU2_0]      2.567034 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_0]      2.568294 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_0]      2.568335 s: FVID2: Init ... !!!
    [MCU2_0]      2.568444 s: FVID2: Init ... Done !!!
    [MCU2_0]      2.568473 s: DSS: Init ... !!!
    [MCU2_0]      2.568495 s: DSS: Display type is eDP !!!
    [MCU2_0]      2.568518 s: DSS: M2M Path is enabled !!!
    [MCU2_0]      2.568540 s: DSS: SoC init ... !!!
    [MCU2_0]      2.568560 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
    [MCU2_0]      2.568717 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.568744 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2
    [MCU2_0]      2.568971 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.568997 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2
    [MCU2_0]      2.569246 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.569274 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2
    [MCU2_0]      2.569417 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.569442 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2
    [MCU2_0]      2.569531 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.569556 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
    [MCU2_0]      2.569677 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.569707 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=158 clk=3 freq=253044000
    [MCU2_0]      2.570694 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
    [MCU2_0]      2.570721 s: SCICLIENT: Sciclient_pmModuleClkRequest module=158 clk=3 state=2 flag=2
    [MCU2_0]      2.571473 s: SCICLIENT: Sciclient_pmModuleClkRequest success
    [MCU2_0]      2.571500 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=2
    [MCU2_0]      2.571839 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.571864 s: DSS: SoC init ... Done !!!
    [MCU2_0]      2.571886 s: DSS: Board init ... !!!
    [MCU2_0]      2.571907 s: DSS: Board init ... Done !!!
    [MCU2_0]      2.593900 s: DSS: Display is not connected
    [MCU2_0]      2.593950 s: DSS: Init ... Done !!!
    [MCU2_0]      2.593973 s: VHWA: VPAC Init ... !!!
    [MCU2_0]      2.593995 s: SCICLIENT: Sciclient_pmSetModuleState module=361 state=2
    [MCU2_0]      2.594235 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.594264 s: VHWA: LDC Init ... !!!
    [MCU2_0]      2.598831 s: VHWA: LDC Init ... Done !!!
    [MCU2_0]      2.598876 s: VHWA: MSC Init ... !!!
    [MCU2_0]      2.611564 s: VHWA: MSC Init ... Done !!!
    [MCU2_0]      2.611598 s: VHWA: NF Init ... !!!
    [MCU2_0]      2.612749 s: VHWA: NF Init ... Done !!!
    [MCU2_0]      2.612782 s: VHWA: VISS Init ... !!!
    [MCU2_0]      2.623954 s: VHWA: VISS Init ... Done !!!
    [MCU2_0]      2.623997 s: VHWA: VPAC Init ... Done !!!
    [MCU2_0]      2.624032 s:  VX_ZONE_INIT:Enabled
    [MCU2_0]      2.624056 s:  VX_ZONE_ERROR:Enabled
    [MCU2_0]      2.624078 s:  VX_ZONE_WARNING:Enabled
    [MCU2_0]      2.625147 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0
    [MCU2_0]      2.625333 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF
    [MCU2_0]      2.625503 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1
    [MCU2_0]      2.625672 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1
    [MCU2_0]      2.625846 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2
    [MCU2_0]      2.626074 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1
    [MCU2_0]      2.626287 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1
    [MCU2_0]      2.626478 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2
    [MCU2_0]      2.626669 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1
    [MCU2_0]      2.626856 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2
    [MCU2_0]      2.627033 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX
    [MCU2_0]      2.627244 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3
    [MCU2_0]      2.627435 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4
    [MCU2_0]      2.627618 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5
    [MCU2_0]      2.627805 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6
    [MCU2_0]      2.627993 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7
    [MCU2_0]      2.628182 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8
    [MCU2_0]      2.628364 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1
    [MCU2_0]      2.628537 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2
    [MCU2_0]      2.628703 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3
    [MCU2_0]      2.628870 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4
    [MCU2_0]      2.629033 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX2
    [MCU2_0]      2.629075 s:  VX_ZONE_INIT:[tivxInitLocal:131] Initialization Done !!!
    [MCU2_0]      2.629104 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_0]      2.655782 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_0]      2.655818 s: CSI2RX: Init ... !!!
    [MCU2_0]      2.655838 s: SCICLIENT: Sciclient_pmSetModuleState module=136 state=2
    [MCU2_0]      2.657436 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.657466 s: SCICLIENT: Sciclient_pmSetModuleState module=38 state=2
    [MCU2_0]      2.658305 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.658332 s: SCICLIENT: Sciclient_pmSetModuleState module=39 state=2
    [MCU2_0]      2.658473 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.658499 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
    [MCU2_0]      2.658601 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.658626 s: SCICLIENT: Sciclient_pmSetModuleState module=153 state=2
    [MCU2_0]      2.658724 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.658892 s: CSI2RX: Init ... Done !!!
    [MCU2_0]      2.658919 s: CSI2TX: Init ... !!!
    [MCU2_0]      2.658940 s: SCICLIENT: Sciclient_pmSetModuleState module=136 state=2
    [MCU2_0]      2.659029 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.659056 s: SCICLIENT: Sciclient_pmSetModuleState module=40 state=2
    [MCU2_0]      2.659182 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.659207 s: SCICLIENT: Sciclient_pmSetModuleState module=41 state=2
    [MCU2_0]      2.659323 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.659350 s: SCICLIENT: Sciclient_pmSetModuleState module=363 state=2
    [MCU2_0]      2.659458 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.659524 s: CSI2TX: Init ... Done !!!
    [MCU2_0]      2.659547 s: ISS: Init ... !!!
    [MCU2_0]      2.659582 s: IssSensor_bl031_Init successful!
    [MCU2_0]      2.659607 s: IssSensor_Init ... Done !!!
    [MCU2_0]      2.659663 s: IttRemoteServer_Init ... Done !!!
    [MCU2_0]      2.659687 s: VISS REMOTE SERVICE: Init ... !!!
    [MCU2_0]      2.659737 s: VISS REMOTE SERVICE: Init ... Done !!!
    [MCU2_0]      2.659763 s: UDMA Copy: Init ... !!!
    [MCU2_0]      2.661907 s: UDMA Copy: Init ... Done !!!
    [MCU2_0]      2.661977 s: APP: Init ... Done !!!
    [MCU2_0]      2.662015 s: SCICLIENT: Sciclient_pmSetModuleState module=219 state=2
    [MCU2_0]      2.662174 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.662201 s: SCICLIENT: Sciclient_pmSetModuleState module=215 state=2
    [MCU2_0]      2.662317 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      2.662356 s: APP: Run ... !!!
    [MCU2_0]      2.662377 s: IPC: Starting echo test ...
    [MCU2_0]      2.664047 s: APP: Run ... Done !!!
    [MCU2_0]      2.664132 s: write 9539 start..........
    [MCU2_0]      2.664298 s: 9539 regAddr[0] = 0xfc status = 0
    [MCU2_0]      2.664463 s: 9539 regAddr[1] = 0xf0 status = 0
    [MCU2_0]      2.664583 s: write 9539 regAddr[6] = 0x0 status = 0
    [MCU2_0]      2.664700 s: write 9539 regAddr[7] = 0xf0 status = 0
    [MCU2_0]      2.665303 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] C7X_1[P] C7X_2[.]
    [MCU2_0]      2.665369 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] C7X_1[P] C7X_2[P]
    [MCU2_0]     12.695276 s:  i2cins: 0x1, addr: 0x6b
    [MCU2_0]     12.695559 s:  DeserializerInit successful
    [MCU2_0]     12.889378 s:                               bl031_Probe, line: 177
    [MCU2_0]     12.889627 s:  :                             bl031_Config, line: 230,  channel: 0
    [MCU2_0]     12.889702 s: max92xx_cfgScript : max92xxI2cAddr = 0x6b
    [MCU2_0]     12.889729 s: max92xx config start
    [MCU2_0]     13.120126 s:  End of max92xx config
    [MCU2_0]     13.170429 s: max96717 map new address 0x40 -> 0x40
    [MCU2_0]     13.170630 s: max96717 config start : slaveAddr = 0x40
    [MCU2_0]     13.247121 s:  End of max96717 config
    [MCU2_0]     13.247500 s:                               bl031_Probe, line: 177
    [MCU2_0]     13.247733 s:  :                             bl031_Config, line: 230,  channel: 1
    [MCU2_0]     13.297431 s: max96717 map new address 0x40 -> 0x41
    [MCU2_0]     13.297635 s: max96717 config start : slaveAddr = 0x41
    [MCU2_0]     13.374122 s:  End of max96717 config
    [MCU2_0]     13.374497 s:                               bl031_Probe, line: 177
    [MCU2_0]     13.374698 s:  :                             bl031_Config, line: 230,  channel: 2
    [MCU2_0]     13.424428 s: max96717 map new address 0x40 -> 0x43
    [MCU2_0]     13.424630 s: max96717 config start : slaveAddr = 0x43
    [MCU2_0]     13.501123 s:  End of max96717 config
    [MCU2_0]     13.501521 s:                               bl031_Probe, line: 177
    [MCU2_0]     13.501736 s:  :                             bl031_Config, line: 230,  channel: 3
    [MCU2_0]     13.551426 s: max96717 map new address 0x40 -> 0x44
    [MCU2_0]     13.551636 s: max96717 config start : slaveAddr = 0x44
    [MCU2_0]     13.628121 s:  End of max96717 config
    [MCU2_0]     13.628882 s:  :                           bl031_StreamOn, line: 309
    [MCU2_0]     13.628952 s: max92xx_cfgScript : max92xxI2cAddr = 0x6b
    [MCU2_0]     13.628982 s: max92xx config start
    [MCU2_0]     13.663123 s:  End of max92xx config
    

    3. vx_app_rtos_linux_mcu2_0.out.map, which corresponds to the compilation result of mcu20.

    vx_app_rtos_linux_mcu2_0.out.map-original

    vx_app_rtos_linux_mcu2_0.out.map-csirx_desc

  • Based on the results of app_status_monitor.out, it appears that about 99% of the original 512KB L3 memory on mcu20 remains unused, and the 256KB available during initialization might be insufficient. However, the csirx desc requires around 190KB (0x30900) and needs at least 192KB to be allocated, so the available resources are a bit tight.

  • Hi Xingyu,

    Yes, its bit tight, but it can still fit, isn't it? If it does not, it would have given the compilation error. Since there is compilation error, it is fitting in the memory. but why CSIRX stopped working? Any change in the sensor/SERDES settings along with this patch? Can we please connect to mcu2_0 using CCS and see where it is getting stuck during initialization? 

    Regards.

    Brijesh

  • dear expert,

              Yes, the memory resource can fit it, no compilation error occured, but mcu2_0 get stuck which we have not figured it out. 

              By the way, NO change in the sensor/SERDES settings along with this  ocram patch.
              We did a test,  change L3_MEM_SIZE from 512KB to 256KB (not add section csirx_desc_mem), mcu2_0 works fine.So L3_MEM_SIZE 256kb should be enough.
              After applying the OCRAM patch,  the app (running in A core) gets stuck in the function ownGraphNodeKernelInit() during the execution of vxVerifyGraph() in tiovx/source/framework/vx_graph_verify.c, which prevents the camera’s initialization and streaming from proceeding. We guess something goes wrong with mcu2_0. We are looking into it  and add more debug info, since we are not quite familiar with CSS tool. 
               
                

  • dear expert,
          After applying the OCRAM patch,  all the file we need to update to the borad is  vx_app_rtos_linux_mcu2_0.out , not need any other file? 

  • Hi zhao li,

    This requires to just change mcu2_0 firmware, as this OCM memory is not used on mcu2_1 or anywhere else. Can you please share the map file for mcu2_0? 

    Regards,

    Brijesh

  • Dear expert,
               I reproduce the stuck issue with demo vx_app_multi_cam.out. After applying the OCRAM patch,  app vx_app_multi_cam.out  also  gets stuck in the function app_verify_graph()  during the execution of vxVerifyGraph() in vision_apps/apps/basic_demos/app_multi_cam/main.c, log listed below:
              

    root@imotion:/opt/vision_apps# ./run_app_multi_cam.sh
    APP: Init ... !!!
    MEM: Init ... !!!
    MEM: Initialized DMA HEAP (fd=4) !!!
    MEM: Init ... Done !!!
    IPC: Init ... !!!
    IPC: Init ... Done !!!
    REMOTE_SERVICE: Init ... !!!
    REMOTE_SERVICE: Init ... Done !!!
        10.391005 s: GTC Frequency = 200 MHz
    APP: Init ... Done !!!
        10.393389 s:  VX_ZONE_INIT:Enabled
        10.393431 s:  VX_ZONE_ERROR:Enabled
        10.393441 s:  VX_ZONE_WARNING:Enabled
        10.394684 s:  VX_ZONE_INIT:[tivxInitLocal:131] Initialization Done !!!
        10.398269 s:  VX_ZONE_INIT:[tivxHostInitLocal:93] Initialization Done for HOST !!!
        10.574241 s: ISS: Enumerating sensors ... !!!
        10.574801 s: ISS: Enumerating sensors ... found 0 : BL_031_3M_96717_SVM
    1 sensor(s) found
    Supported sensor list:
    a : BL_031_3M_96717_SVM
    Select a sensor above or press '0' to autodetect the sensor
    a
    Sensor selected : BL_031_3M_96717_SVM
    Querying BL_031_3M_96717_SVM
        12.035469 s: ISS: Querying sensor [BL_031_3M_96717_SVM] ... !!!
        12.035739 s: ISS: Querying sensor [BL_031_3M_96717_SVM] ... Done !!!
    LDC Selection Yes(1)/No(0)
    Max number of cameras supported by sensor BL_031_3M_96717_SVM = 4
    Please enter number of cameras to be enabled
    4
    YUV Input selected. VISS, AEWB and Mosaic nodes will be bypassed.
    Creating context done!
    Kernel loading done!
        16.447954 s: ISS: Initializing sensor [BL_031_3M_96717_SVM], doing IM_SENSOR_CMD_PWRON ... !!!
        16.448238 s: ISS: Initializing sensor [BL_031_3M_96717_SVM], doing IM_SENSOR_CMD_CONFIG ... !!!
        17.403376 s: ISS: Initializing sensor [BL_031_3M_96717_SVM] ... Done !!!
    Sensor init done!
    Display init done!
    App Init Done!
    Graph create done!
    Capture graph done!
    App Create Graph Done!


            This will be helpfull for you to reproduce the stuck issue after applying the OCRAM patch.

    Regards,
    Zhao Li

  • Hi Zhao Li,

    ok, let me try it on EVM first and share you the changes. 

    Regards,

    Brijesh

  • Dear expert,
           After applying the OCRAM patch, mcu2_0  gets stuck in CSL_udmapCppi5SetDescType(pTrpd, descType)  , right at the beginning of 

    CsirxDrv_udmaRxTrpdInit(),pdk_j721s2_08_06_01_03/packages/ti/drv/csirx/src/csirx_drvUdma.c。

    Regards,
    Zhao Li
  • Hi Zhao Li,

    That's surprising. Can you please check the pTrpd address and see if it is pointing to correct OCM memory? Also can you please check from the CCS memory window if this area is accessible? Most likely this area should be mapped, but if not, can we please add this mapping in the MPU? 

    Regards,

    Brijesh