AM62P: SOC

Hello Juan Wang, 

The waveform is not clear when i save and expand. 

Can you please share a better picture.

juan wang said:

when switching ecu from power off to power on,  Are there any requirements  for each  power suppliers to start at what level min voltage ？

All the supply rails voltage is required to be < 0.3 V 

juan wang said:

4.when switching ecu from power off to power on,  Are there any requirements  for each  power suppliers at  min voltage  for at least what time？

The power-up sequence is required to be followed.

The current supply ramp is expected to start after the previous supply ramps and stabilizes, 

There is no timing requirements between supply ramps.

Regards,

Sreenivasa

hello,Kallikuppa

Thank you for you reply【T476419】Power Down sequence timing_SOC_20250121.xlsx

I add excel file ,pls help to check

Hello Juan Wang, 

Thank you.

Let me review.

Are you using TI Power architecture?

Regards,

Sreenivasa

Are you using TI Power architecture?

→Maybe，It is designed by EU team，I am not very sure （China team）。

Hello Juan Wang, 

Thank you.

The schematics is attached in the excel.

When VDD_CORE is 0.85V, the recommendation is to source the VDD_CORE and VDDR_CORE supply form the same power source.

I suspect you may have to add some load at the output of the load switch or reduce capacitor to make the supply decay faster.

Regards,

Sreenivasa