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Clock inputs to TMS320C6678

maril
Intellectual 560 points
Other Parts Discussed in Thread: CDCE62005, TMS320C6678

Hi All ,

In my custom board i am sourcing the DDR,SYSCLK,PCIeCLK,PASSCLK,MCMCLK of Shannon from CDCE62005 chip. I understand that CDCE62005 requires programming to generate the output clocks. I plan to programm the CDCE chis via SPI port from a host processor. Due to this scheme teh Shannon clcok inputs will be driven with default clock outputs of CDCE chip until it is programmed by teh Host processor. The default outputs of CDCE is violating the clock requirements of Shannon for SRIOCLK and PASSCLK as desribed below :

1) SRIOCLK

Default = 125MHz generated by CDCE

Requirement on Shannon = 156.25 - 312.5 MHz

2) PASSCLK

Default = 125MHz generated by CDCE

Requirement on Shannon = 156.25 - 312.5 MHz

Will this cause any damage to the Shannon processsor. The default clocks are applied momentarily when Shannon is in RESET state ,until the CDCE chip is progrmamed.

I observe that in TMS320C6678 EVM teh PASSCLK sourced to Shannon is 100 MHz which is vialating the requirements on Shannon (156.25 - 312.5 MHz)??

-Anil

  • 0
    Intellectual 560 points

    Hi All ,

    I did some more exploration and observed that in the TMS320C6678 EVM the clock generator (CDCE62005) chip gets programmed by FPGA . The programming happens just after D1V8 supply has stabilized. The sequence followed is :

    1) CDCE is brought out of Power_down (by driving Power_down signal HIGH.)

    2) CDCE is programmed via SPI interface to generate required clock outputs.

    Now , before the CDCE is programmed and after it is brought out of power_down (i.e. between steps 1 and 2 ) the CDCE is outputting default clocks . Some of these clcoks are violating TMSC320C6678 clock requirements . One such clock signal is the SRIOCLK . The requirment for SRIOCLK pin is 156.25-312.5 LVDS whereas teh default clock output by CDCE chip on that pin is 125 MHz LVPECL. Will this violation cause any damage to the chip ?

    -Anil