TMS320C6416T: Request for Length Matching Details - TMS320C6416TBCLZD1

The JTAG peripheral changes signals on the falling edge of TCK and latch signals on the rising edge of TCK. Therefore, you can always resolve any setup time or hold time violations by reducing the frequency of TCK. This eliminates any need to limit or match trace delays as long as you are willing to reduce the operating frequency of the JTAG peripheral.

Some debuggers can be configured to use RTCK as the capture clock for the TDO signal, as a way to compensate for round trip PCB and cable delays. This may allow the JTAG peripheral to operate at a higher frequency. The real benefit is when the target device has a RTC output signal that also compensates for the delay introduced by the target device. The TMS320C6416 device doesn't provide the RTCK output, so one option is looping the TCK signal back to debugger. However, this option can be problematic. The debugger may support a configuration option that uses its own TCK signal as the TDO capture clock rather than the looped back TCK signal. If so, this may be a more reliable option because branching the TCK signal into two paths on the target PCB can introduce signal integrity issues on the TCK signal. It is very important that your PCB design doesn't introduce any signal distortion on the TMS320C6416 TCK input such that it sees non-monotonic transitions. You should simulate signal distortion introduced by your PCB design to confirm your design is robust if you loop the TCK signal back to RTCK.

Regards,
Paul

This device pre-dates my support, so I'm not familiar with any PCB layout references. Use the method described in my answer to #3.

As mentioned in my previous reply, RTCK support may be optional for some debuggers. The RTCK signal was implemented to improve operating speed of the JTAG peripheral, but it may not be required for some debuggers. You will need to ask the debugger manufacture if the RTCK is required for their debugger to operate properly. It is not required by the TMS320C6416 device.

The buffer shown in the schematic snapshot inserted above would need to be placed very close to the TMS320C6416 TCK input pin such that each leg of the signal trace branch is very short and equal length (a short-T clocking topology). You should also include a pull-up on the TCK signal to ensure it is not floating when a debugger is not connected.

Regards,
Paul