Tool/software:
Hi there,
I found a defect listed on the Ti Errata document, the number is i694, which shows as the below:
i694 System I2C Hang Due to Miss of Bus Clear Support
CRITICALITY Low
DESCRIPTION There is no H/W mechanism preventing violating below I2C Bus clear standard
requirement.
If the data line (SDA) is stuck LOW, the master should send 9 clock pulses. The device
that held the bus LOW should release it sometime within those 9 clocks. If not, then use
the HW reset or cycle power to clear the bus.
Sys_Warmreset doesn't reset the I2C IP it does at IC level.
So, once the situation is reached, IC is seeing bus busy status bit.
WORKAROUND I2C SW handler could be programmed to detect such a locked situation. In this case, it
will check the Bus Busy bit and issue the needed clock pulses.
I met the defect on our design, but I couldn't understand the WORKAROUND totally. Is any patch or sample to solve the issue ?
The SDK version what we used is: ti-processor-sdk-linux-am57xx-hs-evm-06.00.00.07-Linux-x86-Install
Best regards,
Pingan
