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TDA4AL-Q1: TDA4AL: can't inialize LPDDR4 1GB at tispl/ uboot( main design LPDDR 8GB ok)

Novasky Yao
Prodigy 170 points
Part Number: TDA4AL-Q1
Other Parts Discussed in Thread: SYSCONFIG, TDA4VL

Tool/software:

z41m_automotive_lpddr4x_lpddr4_MT53E256M32D1KS-046 AUTL.pdf

Fullscreen diff_result.txt Download 
diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi
index c4eb217960..9f9e0c693d 100755
--- a/arch/arm/dts/k3-j721s2-som-p0.dtsi
+++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi
@@ -14,9 +14,9 @@
        memory@80000000 {
                device_type = "memory";
                bootph-all;
-               /* 8 GB RAM */
-               reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-                     <0x00000008 0x80000000 0x00000001 0x80000000>;
+               /* 1 GB RAM */
+               reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
+
        };

        /* Reserving memory regions still pending */

Hi TI experts:

We use 8GB DDR4 to develop, the uboot/kernel can boot normally. Our cost down target HW is 1GB DDR, the datasheet is at the attached file.

I have changed the DDR setting based on sysconfig, and generate k3-j721s2-ddr-evm-lp4.dtsi to replace u-boot/ti-u-boot/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi

but the uboot hang log is as follows, please give us guides

U-Boot MCU SPL 2024.04-ti-g8cba7e9251c8 (Jan 09 2025 - 10:54:18 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
Enable MCU ADC1 as GPI input
MCU_CTRL_MMR_CFG0_MCU_ADC1_CTRL:10001
MCU_ADC1_AIN0 value:0
MCU_ADC1_AIN1 value:0
MCU_ADC1_AIN2 value:0
MCU_ADC1_AIN3 value:0
hwid:0000
hwid:0
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Timeout during frequency handshake
### ERROR ### Please RESET the board ###

  • 0
    Prodigy 170 points

    // @cliArgs --device "J721S2_TDA4VE_TDA4AL_TDA4VL_AM68x" --package "ALZ" --part "Default" --product "TDA4x_DRA8x_AM67x-AM69x_DDR_Config@0.11.00.0000"

    const DDRSS = scripting.addModule("/DDRSS");

    DDRSS.system_cfg_soc_number = "TDA4AL";
    DDRSS.system_cfg_ddrss_active = "DDRSS0 Only";
    DDRSS.system_cfg_dram_type = "LPDDR4";
    DDRSS.system_cfg_msmc_intlv_hybrid = "NA";
    DDRSS.system_cfg_msmc_intlv_size = 1;
    DDRSS.system_cfg_msmc_intlv_gran = "128 B";
    DDRSS.config_fsp0_MHz = 55;
    DDRSS.config_fsp1_MHz = 2133;
    DDRSS.config_fsp2_MHz = 2133;


    DDRSS.lpddr4.system_cfg_dram_width = 32;
    DDRSS.lpddr4.system_cfg_dram_density = 16;
    DDRSS.lpddr4.system_cfg_dram_ranks = 1;
    DDRSS.lpddr4.system_cfg_dram_mr4_poll = "No";
    DDRSS.lpddr4.system_cfg_sys_temp_grad = 30;
    DDRSS.lpddr4.config_dram_mr1_rd_pre_FS2 = "Static";
    DDRSS.lpddr4.config_dram_mr1_rd_pst_FS2 = "1.5 x tCK";
    DDRSS.lpddr4.config_dram_mr3_wr_pst_FS2 = "1.5 x tCK";
    DDRSS.lpddr4.config_dram_mr3_dbi_rd_FS2 = "Disable";
    DDRSS.lpddr4.config_dram_mr3_dbi_wr_FS2 = "Enable";
    DDRSS.lpddr4.config_dram_mr2_rl_FS2 = 36;
    DDRSS.lpddr4.config_dram_mr2_wls_FS2 = "WL set A";
    DDRSS.lpddr4.config_dram_mr2_wl_FS2 = 18;
    DDRSS.lpddr4.config_dram_mr1_nWR_FS2 = 40;
    DDRSS.lpddr4.config_dram_odtlon_FS2 = 8;
    DDRSS.lpddr4.config_dram_odtloff_FS2 = 28;
    DDRSS.lpddr4.config_dram_tINIT1_tCK = "";
    DDRSS.lpddr4.config_dram_tINIT1_ns = 200000;
    DDRSS.lpddr4.config_dram_tINIT2_tCK = "";
    DDRSS.lpddr4.config_dram_tINIT2_ns = 10;
    DDRSS.lpddr4.config_dram_tINIT3_tCK = "";
    DDRSS.lpddr4.config_dram_tINIT3_ns = 2000000;
    DDRSS.lpddr4.config_dram_tINIT4_tCK = 5;
    DDRSS.lpddr4.config_dram_tINIT4_ns = "";
    DDRSS.lpddr4.config_dram_tINIT5_tCK = "";
    DDRSS.lpddr4.config_dram_tINIT5_ns = 2000;
    DDRSS.lpddr4.config_dram_tPW_RESET_tCK = "";
    DDRSS.lpddr4.config_dram_tPW_RESET_ns = 100;
    DDRSS.lpddr4.config_dram_tREFIab_tCK = "";
    DDRSS.lpddr4.config_dram_tREFIab_ns = 1950;
    DDRSS.lpddr4.config_dram_tREFIpb_tCK = "";
    DDRSS.lpddr4.config_dram_tREFIpb_ns = 488;
    DDRSS.lpddr4.config_dram_tRFCab_tCK = "";
    DDRSS.lpddr4.config_dram_tRFCab_ns = 380;
    DDRSS.lpddr4.config_dram_tRFCpb_tCK = "";
    DDRSS.lpddr4.config_dram_tRFCpb_ns = 190;
    DDRSS.lpddr4.config_dram_tVRCG_ENABLE_tCK = "";
    DDRSS.lpddr4.config_dram_tVRCG_ENABLE_ns = 200;
    DDRSS.lpddr4.config_dram_tVRCG_DISABLE_tCK = "";
    DDRSS.lpddr4.config_dram_tVRCG_DISABLE_ns = 100;
    DDRSS.lpddr4.config_dram_tOSCO_tCK = 8;
    DDRSS.lpddr4.config_dram_tOSCO_ns = 40;
    DDRSS.lpddr4.config_dram_tZQCAL_tCK = "";
    DDRSS.lpddr4.config_dram_tZQCAL_ns = 1000;
    DDRSS.lpddr4.config_dram_tZQLAT_tCK = 8;
    DDRSS.lpddr4.config_dram_tZQLAT_ns = 30;
    DDRSS.lpddr4.config_dram_tZQRESET_tCK = 3;
    DDRSS.lpddr4.config_dram_tZQRESET_ns = 50;
    DDRSS.lpddr4.config_dram_tFClong_tCK = "";
    DDRSS.lpddr4.config_dram_tFClong_ns = 250;
    DDRSS.lpddr4.config_dram_tCKFSPE_tCK = 4;
    DDRSS.lpddr4.config_dram_tCKFSPE_ns = 7.5;
    DDRSS.lpddr4.config_dram_tCKFSPX_tCK = 4;
    DDRSS.lpddr4.config_dram_tCKFSPX_ns = 7.5;
    DDRSS.lpddr4.config_dram_tDQSCKmin_tCK = "";
    DDRSS.lpddr4.config_dram_tDQSCKmin_ns = 1.5;
    DDRSS.lpddr4.config_dram_tDQSCKmax_tCK = "";
    DDRSS.lpddr4.config_dram_tDQSCKmax_ns = 3.6;
    DDRSS.lpddr4.config_dram_tCKE_tCK = 4;
    DDRSS.lpddr4.config_dram_tCKE_ns = 7.5;
    DDRSS.lpddr4.config_dram_tCMDCKE_tCK = 3;
    DDRSS.lpddr4.config_dram_tCMDCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram_tCKELCK_tCK = 5;
    DDRSS.lpddr4.config_dram_tCKELCK_ns = 5;
    DDRSS.lpddr4.config_dram_tCSCKE_tCK = "";
    DDRSS.lpddr4.config_dram_tCSCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram_tCKELCS_tCK = 5;
    DDRSS.lpddr4.config_dram_tCKELCS_ns = 5;
    DDRSS.lpddr4.config_dram_tCKCKEH_tCK = 3;
    DDRSS.lpddr4.config_dram_tCKCKEH_ns = 1.75;
    DDRSS.lpddr4.config_dram_tXP_tCK = 5;
    DDRSS.lpddr4.config_dram_tXP_ns = 7.5;
    DDRSS.lpddr4.config_dram_tCSCKEH_tCK = "";
    DDRSS.lpddr4.config_dram_tCSCKEH_ns = 1.75;
    DDRSS.lpddr4.config_dram_tCKEHCS_tCK = 5;
    DDRSS.lpddr4.config_dram_tCKEHCS_ns = 7.5;
    DDRSS.lpddr4.config_dram_tMRWCKEL_tCK = 10;
    DDRSS.lpddr4.config_dram_tMRWCKEL_ns = 14;
    DDRSS.lpddr4.config_dram_tZQCKE_tCK = 3;
    DDRSS.lpddr4.config_dram_tZQCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram_tMRW_tCK = 10;
    DDRSS.lpddr4.config_dram_tMRW_ns = 10;
    DDRSS.lpddr4.config_dram_tMRD_tCK = 10;
    DDRSS.lpddr4.config_dram_tMRD_ns = 14;
    DDRSS.lpddr4.config_dram_tMRR_tCK = 8;
    DDRSS.lpddr4.config_dram_tMRR_ns = "";
    DDRSS.lpddr4.config_dram_tMRRI_tCK = 3;
    DDRSS.lpddr4.config_dram_tMRRI_ns = "";
    DDRSS.lpddr4.config_dram_tSDO_tCK = 12;
    DDRSS.lpddr4.config_dram_tSDO_ns = 20;
    DDRSS.lpddr4.config_dram_tRC_tCK = "Auto Calc: tRAS + tRP";
    DDRSS.lpddr4.config_dram_tRC_ns = "";
    DDRSS.lpddr4.config_dram_tSR_tCK = 3;
    DDRSS.lpddr4.config_dram_tSR_ns = 15;
    DDRSS.lpddr4.config_dram_tXSR_tCK = 2;
    DDRSS.lpddr4.config_dram_tXSR_ns = 387.5;
    DDRSS.lpddr4.config_dram_tCCD_tCK = 8;
    DDRSS.lpddr4.config_dram_tCCD_ns = "";
    DDRSS.lpddr4.config_dram_tCCDMW_tCK = 32;
    DDRSS.lpddr4.config_dram_tCCDMW_ns = "";
    DDRSS.lpddr4.config_dram_tRTP_tCK = 8;
    DDRSS.lpddr4.config_dram_tRTP_ns = 7.5;
    DDRSS.lpddr4.config_dram_tRCD_tCK = 4;
    DDRSS.lpddr4.config_dram_tRCD_ns = 19.875;
    DDRSS.lpddr4.config_dram_tRPpb_tCK = 4;
    DDRSS.lpddr4.config_dram_tRPpb_ns = 19.875;
    DDRSS.lpddr4.config_dram_tRPab_tCK = 4;
    DDRSS.lpddr4.config_dram_tRPab_ns = 22.875;
    DDRSS.lpddr4.config_dram_tRASmin_tCK = 3;
    DDRSS.lpddr4.config_dram_tRASmin_ns = 43.875;
    DDRSS.lpddr4.config_dram_tRASmax_tCK = "";
    DDRSS.lpddr4.config_dram_tRASmax_ns = 17550;
    DDRSS.lpddr4.config_dram_tWR_tCK = 4;
    DDRSS.lpddr4.config_dram_tWR_ns = 18;
    DDRSS.lpddr4.config_dram_tWTR_tCK = 8;
    DDRSS.lpddr4.config_dram_tWTR_ns = 10;
    DDRSS.lpddr4.config_dram_tRRD_tCK = 4;
    DDRSS.lpddr4.config_dram_tRRD_ns = 9.375;
    DDRSS.lpddr4.config_dram_tPPD_tCK = 4;
    DDRSS.lpddr4.config_dram_tPPD_ns = "";
    DDRSS.lpddr4.config_dram_tFAW_tCK = "";
    DDRSS.lpddr4.config_dram_tFAW_ns = 30;
    DDRSS.lpddr4.config_dram_tESCKE_tCK = 3;
    DDRSS.lpddr4.config_dram_tESCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram_tDStrain_tCK = "";
    DDRSS.lpddr4.config_dram_tDStrain_ns = 2;
    DDRSS.lpddr4.config_dram_tADR_tCK = "";
    DDRSS.lpddr4.config_dram_tADR_ns = 20;
    DDRSS.lpddr4.config_dram_tCAENT_tCK = "";
    DDRSS.lpddr4.config_dram_tCAENT_ns = 250;
    DDRSS.lpddr4.config_dram_tVREFcalong_tCK = "";
    DDRSS.lpddr4.config_dram_tVREFcalong_ns = 250;
    DDRSS.lpddr4.config_dram_tVREFcashort_tCK = "";
    DDRSS.lpddr4.config_dram_tVREFcashort_ns = 80;
    DDRSS.lpddr4.config_dram_tCKEHDQS_tCK = "";
    DDRSS.lpddr4.config_dram_tCKEHDQS_ns = 10;
    DDRSS.lpddr4.config_dram_tMRZ_tCK = "";
    DDRSS.lpddr4.config_dram_tMRZ_ns = 1.5;
    DDRSS.lpddr4.config_dram_tODTonMIN_tCK = "";
    DDRSS.lpddr4.config_dram_tODTonMIN_ns = 1.5;
    DDRSS.lpddr4.config_dram_tODTonMAX_tCK = "";
    DDRSS.lpddr4.config_dram_tODTonMAX_ns = 3.5;
    DDRSS.lpddr4.config_dram_tODToffMIN_tCK = "";
    DDRSS.lpddr4.config_dram_tODToffMIN_ns = 1.5;
    DDRSS.lpddr4.config_dram_tODToffMAX_tCK = "";
    DDRSS.lpddr4.config_dram_tODToffMAX_ns = 3.5;
    DDRSS.lpddr4.config_dram_tTSI_tCK = "";
    DDRSS.lpddr4.config_dram_tTSI_ns = 32000000;
    DDRSS.lpddr4.config_dram_TempMargin_tCK = "";
    DDRSS.lpddr4.config_dram_TempMargin_ns = 2;
    DDRSS.lpddr4.config_io_cell_mode_dl0 = "Range 0";
    DDRSS.lpddr4.config_io_cell_vrefsel_dl0 = 16.7;
    DDRSS.lpddr4.config_io_cell_enslicen_drv_dl0_dq = "40 Ohm";
    DDRSS.lpddr4.config_io_cell_enslicen_drv_dl0_dqs = "40 Ohm";
    DDRSS.lpddr4.config_io_cell_enslicen_drv_ac = "40 Ohm";
    DDRSS.lpddr4.config_io_cell_enslicen_drv_cs = "80 Ohm";
    DDRSS.lpddr4.config_io_cell_enslicen_odt_dl0_dq = "40 Ohm";
    DDRSS.lpddr4.config_io_cell_enslicen_odt_dl0_dqs = "40 Ohm";
    DDRSS.lpddr4.config_dram_mr14_vr_dq_FS0 = "Range 0";
    DDRSS.lpddr4.config_dram_mr14_vref_dq_FS0 = 10;
    DDRSS.lpddr4.config_dram_mr12_vr_ca_FS0 = "Range 0";
    DDRSS.lpddr4.config_dram_mr12_vref_ca_FS0 = 10;
    DDRSS.lpddr4.config_dram_mr11_ca_odt_FS0 = "Disable";
    DDRSS.lpddr4.config_dram_mr11_dq_odt_FS0 = "Disable";
    DDRSS.lpddr4.config_dram_mr14_vr_dq_FS2 = "Range 0";
    DDRSS.lpddr4.config_dram_mr14_vref_dq_FS2 = 16;
    DDRSS.lpddr4.config_dram_mr12_vr_ca_FS2 = "Range 0";
    DDRSS.lpddr4.config_dram_mr12_vref_ca_FS2 = 25.6;
    DDRSS.lpddr4.config_dram_mr11_ca_odt_FS2 = "RZQ/3";
    DDRSS.lpddr4.config_dram_mr11_dq_odt_FS2 = "RZQ/6";
    DDRSS.lpddr4.config_dram_mr3_pdds_FS2 = "RZQ/6";
    DDRSS.lpddr4.config_dram_mr3_pu_cal_FS2 = "VDDQ / 3";
    DDRSS.lpddr4.config_dram_mr22_odtd_ca_FS2 = "ODT_CA Bond Pad";
    DDRSS.lpddr4.config_dram_mr22_odte_ck_FS2 = "Disable";
    DDRSS.lpddr4.config_dram_mr22_odte_cs_FS2 = "Enable";
    DDRSS.lpddr4.config_dram_mr22_soc_odt_FS2 = "RZQ/6";
    DDRSS.lpddr4.system_cfg_dram1_width = 32;
    DDRSS.lpddr4.system_cfg_dram1_density = 16;
    DDRSS.lpddr4.system_cfg_dram1_ranks = 2;
    DDRSS.lpddr4.system_cfg_dram1_mr4_poll = "No";
    DDRSS.lpddr4.system_cfg_sys_temp_grad1 = 30;
    DDRSS.lpddr4.config_dram1_mr1_rd_pre_FS2 = "Static";
    DDRSS.lpddr4.config_dram1_mr1_rd_pst_FS2 = "1.5 x tCK";
    DDRSS.lpddr4.config_dram1_mr3_wr_pst_FS2 = "1.5 x tCK";
    DDRSS.lpddr4.config_dram1_mr3_dbi_rd_FS2 = "Enable";
    DDRSS.lpddr4.config_dram1_mr3_dbi_wr_FS2 = "Enable";
    DDRSS.lpddr4.config_dram1_mr2_rl_FS2 = 40;
    DDRSS.lpddr4.config_dram1_mr2_wls_FS2 = "WL set A";
    DDRSS.lpddr4.config_dram1_mr2_wl_FS2 = 18;
    DDRSS.lpddr4.config_dram1_mr1_nWR_FS2 = 40;
    DDRSS.lpddr4.config_dram1_odtlon_FS2 = 8;
    DDRSS.lpddr4.config_dram1_odtloff_FS2 = 28;
    DDRSS.lpddr4.config_dram1_tINIT1_tCK = "";
    DDRSS.lpddr4.config_dram1_tINIT1_ns = 200000;
    DDRSS.lpddr4.config_dram1_tINIT2_tCK = "";
    DDRSS.lpddr4.config_dram1_tINIT2_ns = 10;
    DDRSS.lpddr4.config_dram1_tINIT3_tCK = "";
    DDRSS.lpddr4.config_dram1_tINIT3_ns = 2000000;
    DDRSS.lpddr4.config_dram1_tINIT4_tCK = 5;
    DDRSS.lpddr4.config_dram1_tINIT4_ns = "";
    DDRSS.lpddr4.config_dram1_tINIT5_tCK = "";
    DDRSS.lpddr4.config_dram1_tINIT5_ns = 2000;
    DDRSS.lpddr4.config_dram1_tPW_RESET_tCK = "";
    DDRSS.lpddr4.config_dram1_tPW_RESET_ns = 100;
    DDRSS.lpddr4.config_dram1_tREFIab_tCK = "";
    DDRSS.lpddr4.config_dram1_tREFIab_ns = 1950;
    DDRSS.lpddr4.config_dram1_tREFIpb_tCK = "";
    DDRSS.lpddr4.config_dram1_tREFIpb_ns = 488;
    DDRSS.lpddr4.config_dram1_tRFCab_tCK = "";
    DDRSS.lpddr4.config_dram1_tRFCab_ns = 380;
    DDRSS.lpddr4.config_dram1_tRFCpb_tCK = "";
    DDRSS.lpddr4.config_dram1_tRFCpb_ns = 190;
    DDRSS.lpddr4.config_dram1_tVRCG_ENABLE_tCK = "";
    DDRSS.lpddr4.config_dram1_tVRCG_ENABLE_ns = 200;
    DDRSS.lpddr4.config_dram1_tVRCG_DISABLE_tCK = "";
    DDRSS.lpddr4.config_dram1_tVRCG_DISABLE_ns = 100;
    DDRSS.lpddr4.config_dram1_tOSCO_tCK = 8;
    DDRSS.lpddr4.config_dram1_tOSCO_ns = 40;
    DDRSS.lpddr4.config_dram1_tZQCAL_tCK = "";
    DDRSS.lpddr4.config_dram1_tZQCAL_ns = 1000;
    DDRSS.lpddr4.config_dram1_tZQLAT_tCK = 8;
    DDRSS.lpddr4.config_dram1_tZQLAT_ns = 30;
    DDRSS.lpddr4.config_dram1_tZQRESET_tCK = 3;
    DDRSS.lpddr4.config_dram1_tZQRESET_ns = 50;
    DDRSS.lpddr4.config_dram1_tFClong_tCK = "";
    DDRSS.lpddr4.config_dram1_tFClong_ns = 250;
    DDRSS.lpddr4.config_dram1_tCKFSPE_tCK = 4;
    DDRSS.lpddr4.config_dram1_tCKFSPE_ns = 7.5;
    DDRSS.lpddr4.config_dram1_tCKFSPX_tCK = 4;
    DDRSS.lpddr4.config_dram1_tCKFSPX_ns = 7.5;
    DDRSS.lpddr4.config_dram1_tDQSCKmin_tCK = "";
    DDRSS.lpddr4.config_dram1_tDQSCKmin_ns = 1.5;
    DDRSS.lpddr4.config_dram1_tDQSCKmax_tCK = "";
    DDRSS.lpddr4.config_dram1_tDQSCKmax_ns = 3.6;
    DDRSS.lpddr4.config_dram1_tCKE_tCK = 4;
    DDRSS.lpddr4.config_dram1_tCKE_ns = 7.5;
    DDRSS.lpddr4.config_dram1_tCMDCKE_tCK = 3;
    DDRSS.lpddr4.config_dram1_tCMDCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram1_tCKELCK_tCK = 5;
    DDRSS.lpddr4.config_dram1_tCKELCK_ns = 5;
    DDRSS.lpddr4.config_dram1_tCSCKE_tCK = "";
    DDRSS.lpddr4.config_dram1_tCSCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram1_tCKELCS_tCK = 5;
    DDRSS.lpddr4.config_dram1_tCKELCS_ns = 5;
    DDRSS.lpddr4.config_dram1_tCKCKEH_tCK = 3;
    DDRSS.lpddr4.config_dram1_tCKCKEH_ns = 1.75;
    DDRSS.lpddr4.config_dram1_tXP_tCK = 5;
    DDRSS.lpddr4.config_dram1_tXP_ns = 7.5;
    DDRSS.lpddr4.config_dram1_tCSCKEH_tCK = "";
    DDRSS.lpddr4.config_dram1_tCSCKEH_ns = 1.75;
    DDRSS.lpddr4.config_dram1_tCKEHCS_tCK = 5;
    DDRSS.lpddr4.config_dram1_tCKEHCS_ns = 7.5;
    DDRSS.lpddr4.config_dram1_tMRWCKEL_tCK = 10;
    DDRSS.lpddr4.config_dram1_tMRWCKEL_ns = 14;
    DDRSS.lpddr4.config_dram1_tZQCKE_tCK = 3;
    DDRSS.lpddr4.config_dram1_tZQCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram1_tMRW_tCK = 10;
    DDRSS.lpddr4.config_dram1_tMRW_ns = 10;
    DDRSS.lpddr4.config_dram1_tMRD_tCK = 10;
    DDRSS.lpddr4.config_dram1_tMRD_ns = 14;
    DDRSS.lpddr4.config_dram1_tMRR_tCK = 8;
    DDRSS.lpddr4.config_dram1_tMRR_ns = "";
    DDRSS.lpddr4.config_dram1_tMRRI_tCK = 3;
    DDRSS.lpddr4.config_dram1_tMRRI_ns = "";
    DDRSS.lpddr4.config_dram1_tSDO_tCK = 12;
    DDRSS.lpddr4.config_dram1_tSDO_ns = 20;
    DDRSS.lpddr4.config_dram1_tRC_tCK = "Auto Calc: tRAS + tRP";
    DDRSS.lpddr4.config_dram1_tRC_ns = "";
    DDRSS.lpddr4.config_dram1_tSR_tCK = 3;
    DDRSS.lpddr4.config_dram1_tSR_ns = 15;
    DDRSS.lpddr4.config_dram1_tXSR_tCK = 2;
    DDRSS.lpddr4.config_dram1_tXSR_ns = 387.5;
    DDRSS.lpddr4.config_dram1_tCCD_tCK = 8;
    DDRSS.lpddr4.config_dram1_tCCD_ns = "";
    DDRSS.lpddr4.config_dram1_tCCDMW_tCK = 32;
    DDRSS.lpddr4.config_dram1_tCCDMW_ns = "";
    DDRSS.lpddr4.config_dram1_tRTP_tCK = 8;
    DDRSS.lpddr4.config_dram1_tRTP_ns = 7.5;
    DDRSS.lpddr4.config_dram1_tRCD_tCK = 4;
    DDRSS.lpddr4.config_dram1_tRCD_ns = 19.875;
    DDRSS.lpddr4.config_dram1_tRPpb_tCK = 4;
    DDRSS.lpddr4.config_dram1_tRPpb_ns = 19.875;
    DDRSS.lpddr4.config_dram1_tRPab_tCK = 4;
    DDRSS.lpddr4.config_dram1_tRPab_ns = 22.875;
    DDRSS.lpddr4.config_dram1_tRASmin_tCK = 3;
    DDRSS.lpddr4.config_dram1_tRASmin_ns = 43.875;
    DDRSS.lpddr4.config_dram1_tRASmax_tCK = "";
    DDRSS.lpddr4.config_dram1_tRASmax_ns = 17550;
    DDRSS.lpddr4.config_dram1_tWR_tCK = 4;
    DDRSS.lpddr4.config_dram1_tWR_ns = 18;
    DDRSS.lpddr4.config_dram1_tWTR_tCK = 8;
    DDRSS.lpddr4.config_dram1_tWTR_ns = 10;
    DDRSS.lpddr4.config_dram1_tRRD_tCK = 4;
    DDRSS.lpddr4.config_dram1_tRRD_ns = 9.375;
    DDRSS.lpddr4.config_dram1_tPPD_tCK = 4;
    DDRSS.lpddr4.config_dram1_tPPD_ns = "";
    DDRSS.lpddr4.config_dram1_tFAW_tCK = "";
    DDRSS.lpddr4.config_dram1_tFAW_ns = 30;
    DDRSS.lpddr4.config_dram1_tESCKE_tCK = 3;
    DDRSS.lpddr4.config_dram1_tESCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram1_tDStrain_tCK = "";
    DDRSS.lpddr4.config_dram1_tDStrain_ns = 2;
    DDRSS.lpddr4.config_dram1_tADR_tCK = "";
    DDRSS.lpddr4.config_dram1_tADR_ns = 20;
    DDRSS.lpddr4.config_dram1_tCAENT_tCK = "";
    DDRSS.lpddr4.config_dram1_tCAENT_ns = 250;
    DDRSS.lpddr4.config_dram1_tVREFcalong_tCK = "";
    DDRSS.lpddr4.config_dram1_tVREFcalong_ns = 250;
    DDRSS.lpddr4.config_dram1_tVREFcashort_tCK = "";
    DDRSS.lpddr4.config_dram1_tVREFcashort_ns = 80;
    DDRSS.lpddr4.config_dram1_tCKEHDQS_tCK = "";
    DDRSS.lpddr4.config_dram1_tCKEHDQS_ns = 10;
    DDRSS.lpddr4.config_dram1_tMRZ_tCK = "";
    DDRSS.lpddr4.config_dram1_tMRZ_ns = 1.5;
    DDRSS.lpddr4.config_dram1_tODTonMIN_tCK = "";
    DDRSS.lpddr4.config_dram1_tODTonMIN_ns = 1.5;
    DDRSS.lpddr4.config_dram1_tODTonMAX_tCK = "";
    DDRSS.lpddr4.config_dram1_tODTonMAX_ns = 3.5;
    DDRSS.lpddr4.config_dram1_tODToffMIN_tCK = "";
    DDRSS.lpddr4.config_dram1_tODToffMIN_ns = 1.5;
    DDRSS.lpddr4.config_dram1_tODToffMAX_tCK = "";
    DDRSS.lpddr4.config_dram1_tODToffMAX_ns = 3.5;
    DDRSS.lpddr4.config_dram1_tTSI_tCK = "";
    DDRSS.lpddr4.config_dram1_tTSI_ns = 32000000;
    DDRSS.lpddr4.config_dram1_TempMargin_tCK = "";
    DDRSS.lpddr4.config_dram1_TempMargin_ns = 2;
    DDRSS.lpddr4.config_ddr1_io_cell_mode_dl0 = "Range 0";
    DDRSS.lpddr4.config_ddr1_io_cell_vrefsel_dl0 = 16.7;
    DDRSS.lpddr4.config_ddr1_io_cell_enslicen_drv_dl0_dq = "40 Ohm";
    DDRSS.lpddr4.config_ddr1_io_cell_enslicen_drv_dl0_dqs = "40 Ohm";
    DDRSS.lpddr4.config_ddr1_io_cell_enslicen_drv_ac = "40 Ohm";
    DDRSS.lpddr4.config_ddr1_io_cell_enslicen_drv_cs = "80 Ohm";
    DDRSS.lpddr4.config_ddr1_io_cell_enslicen_odt_dl0_dq = "40 Ohm";
    DDRSS.lpddr4.config_ddr1_io_cell_enslicen_odt_dl0_dqs = "40 Ohm";
    DDRSS.lpddr4.config_dram1_mr14_vr_dq_FS0 = "Range 0";
    DDRSS.lpddr4.config_dram1_mr14_vref_dq_FS0 = 10;
    DDRSS.lpddr4.config_dram1_mr12_vr_ca_FS0 = "Range 0";
    DDRSS.lpddr4.config_dram1_mr12_vref_ca_FS0 = 10;
    DDRSS.lpddr4.config_dram1_mr11_ca_odt_FS0 = "Disable";
    DDRSS.lpddr4.config_dram1_mr11_dq_odt_FS0 = "Disable";
    DDRSS.lpddr4.config_dram1_mr14_vr_dq_FS2 = "Range 0";
    DDRSS.lpddr4.config_dram1_mr14_vref_dq_FS2 = 16;
    DDRSS.lpddr4.config_dram1_mr12_vr_ca_FS2 = "Range 0";
    DDRSS.lpddr4.config_dram1_mr12_vref_ca_FS2 = 25.6;
    DDRSS.lpddr4.config_dram1_mr11_ca_odt_FS2 = "RZQ/3";
    DDRSS.lpddr4.config_dram1_mr11_dq_odt_FS2 = "RZQ/6";
    DDRSS.lpddr4.config_dram1_mr3_pdds_FS2 = "RZQ/6";
    DDRSS.lpddr4.config_dram1_mr3_pu_cal_FS2 = "VDDQ / 3";
    DDRSS.lpddr4.config_dram1_mr22_odtd_ca_FS2 = "ODT_CA Bond Pad";
    DDRSS.lpddr4.config_dram1_mr22_odte_ck_FS2 = "Disable";
    DDRSS.lpddr4.config_dram1_mr22_odte_cs_FS2 = "Enable";
    DDRSS.lpddr4.config_dram1_mr22_soc_odt_FS2 = "RZQ/6";
    DDRSS.lpddr4.system_cfg_dram2_width = 32;
    DDRSS.lpddr4.system_cfg_dram2_density = 16;
    DDRSS.lpddr4.system_cfg_dram2_ranks = 2;
    DDRSS.lpddr4.system_cfg_dram2_mr4_poll = "No";
    DDRSS.lpddr4.system_cfg_sys_temp_grad2 = 30;
    DDRSS.lpddr4.config_dram2_mr1_rd_pre_FS2 = "Static";
    DDRSS.lpddr4.config_dram2_mr1_rd_pst_FS2 = "1.5 x tCK";
    DDRSS.lpddr4.config_dram2_mr3_wr_pst_FS2 = "1.5 x tCK";
    DDRSS.lpddr4.config_dram2_mr3_dbi_rd_FS2 = "Disable";
    DDRSS.lpddr4.config_dram2_mr3_dbi_wr_FS2 = "Disable";
    DDRSS.lpddr4.config_dram2_mr2_rl_FS2 = 36;
    DDRSS.lpddr4.config_dram2_mr2_wls_FS2 = "WL set A";
    DDRSS.lpddr4.config_dram2_mr2_wl_FS2 = 18;
    DDRSS.lpddr4.config_dram2_mr1_nWR_FS2 = 40;
    DDRSS.lpddr4.config_dram2_odtlon_FS2 = 8;
    DDRSS.lpddr4.config_dram2_odtloff_FS2 = 28;
    DDRSS.lpddr4.config_dram2_tINIT1_tCK = "";
    DDRSS.lpddr4.config_dram2_tINIT1_ns = 200000;
    DDRSS.lpddr4.config_dram2_tINIT2_tCK = "";
    DDRSS.lpddr4.config_dram2_tINIT2_ns = 10;
    DDRSS.lpddr4.config_dram2_tINIT3_tCK = "";
    DDRSS.lpddr4.config_dram2_tINIT3_ns = 2000000;
    DDRSS.lpddr4.config_dram2_tINIT4_tCK = 5;
    DDRSS.lpddr4.config_dram2_tINIT4_ns = "";
    DDRSS.lpddr4.config_dram2_tINIT5_tCK = "";
    DDRSS.lpddr4.config_dram2_tINIT5_ns = 2000;
    DDRSS.lpddr4.config_dram2_tPW_RESET_tCK = "";
    DDRSS.lpddr4.config_dram2_tPW_RESET_ns = 100;
    DDRSS.lpddr4.config_dram2_tREFIab_tCK = "";
    DDRSS.lpddr4.config_dram2_tREFIab_ns = 3900;
    DDRSS.lpddr4.config_dram2_tREFIpb_tCK = "";
    DDRSS.lpddr4.config_dram2_tREFIpb_ns = 488;
    DDRSS.lpddr4.config_dram2_tRFCab_tCK = "";
    DDRSS.lpddr4.config_dram2_tRFCab_ns = 380;
    DDRSS.lpddr4.config_dram2_tRFCpb_tCK = "";
    DDRSS.lpddr4.config_dram2_tRFCpb_ns = 190;
    DDRSS.lpddr4.config_dram2_tVRCG_ENABLE_tCK = "";
    DDRSS.lpddr4.config_dram2_tVRCG_ENABLE_ns = 200;
    DDRSS.lpddr4.config_dram2_tVRCG_DISABLE_tCK = "";
    DDRSS.lpddr4.config_dram2_tVRCG_DISABLE_ns = 100;
    DDRSS.lpddr4.config_dram2_tOSCO_tCK = 8;
    DDRSS.lpddr4.config_dram2_tOSCO_ns = 40;
    DDRSS.lpddr4.config_dram2_tZQCAL_tCK = "";
    DDRSS.lpddr4.config_dram2_tZQCAL_ns = 1000;
    DDRSS.lpddr4.config_dram2_tZQLAT_tCK = 8;
    DDRSS.lpddr4.config_dram2_tZQLAT_ns = 30;
    DDRSS.lpddr4.config_dram2_tZQRESET_tCK = 3;
    DDRSS.lpddr4.config_dram2_tZQRESET_ns = 50;
    DDRSS.lpddr4.config_dram2_tFClong_tCK = "";
    DDRSS.lpddr4.config_dram2_tFClong_ns = 250;
    DDRSS.lpddr4.config_dram2_tCKFSPE_tCK = 4;
    DDRSS.lpddr4.config_dram2_tCKFSPE_ns = 7.5;
    DDRSS.lpddr4.config_dram2_tCKFSPX_tCK = 4;
    DDRSS.lpddr4.config_dram2_tCKFSPX_ns = 7.5;
    DDRSS.lpddr4.config_dram2_tDQSCKmin_tCK = "";
    DDRSS.lpddr4.config_dram2_tDQSCKmin_ns = 1.5;
    DDRSS.lpddr4.config_dram2_tDQSCKmax_tCK = "";
    DDRSS.lpddr4.config_dram2_tDQSCKmax_ns = 3.6;
    DDRSS.lpddr4.config_dram2_tCKE_tCK = 4;
    DDRSS.lpddr4.config_dram2_tCKE_ns = 7.5;
    DDRSS.lpddr4.config_dram2_tCMDCKE_tCK = 3;
    DDRSS.lpddr4.config_dram2_tCMDCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram2_tCKELCK_tCK = 5;
    DDRSS.lpddr4.config_dram2_tCKELCK_ns = 5;
    DDRSS.lpddr4.config_dram2_tCSCKE_tCK = "";
    DDRSS.lpddr4.config_dram2_tCSCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram2_tCKELCS_tCK = 5;
    DDRSS.lpddr4.config_dram2_tCKELCS_ns = 5;
    DDRSS.lpddr4.config_dram2_tCKCKEH_tCK = 3;
    DDRSS.lpddr4.config_dram2_tCKCKEH_ns = 1.75;
    DDRSS.lpddr4.config_dram2_tXP_tCK = 5;
    DDRSS.lpddr4.config_dram2_tXP_ns = 7.5;
    DDRSS.lpddr4.config_dram2_tCSCKEH_tCK = "";
    DDRSS.lpddr4.config_dram2_tCSCKEH_ns = 1.75;
    DDRSS.lpddr4.config_dram2_tCKEHCS_tCK = 5;
    DDRSS.lpddr4.config_dram2_tCKEHCS_ns = 7.5;
    DDRSS.lpddr4.config_dram2_tMRWCKEL_tCK = 10;
    DDRSS.lpddr4.config_dram2_tMRWCKEL_ns = 14;
    DDRSS.lpddr4.config_dram2_tZQCKE_tCK = 3;
    DDRSS.lpddr4.config_dram2_tZQCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram2_tMRW_tCK = 10;
    DDRSS.lpddr4.config_dram2_tMRW_ns = 10;
    DDRSS.lpddr4.config_dram2_tMRD_tCK = 10;
    DDRSS.lpddr4.config_dram2_tMRD_ns = 14;
    DDRSS.lpddr4.config_dram2_tMRR_tCK = 8;
    DDRSS.lpddr4.config_dram2_tMRR_ns = "";
    DDRSS.lpddr4.config_dram2_tMRRI_tCK = 3;
    DDRSS.lpddr4.config_dram2_tMRRI_ns = "";
    DDRSS.lpddr4.config_dram2_tSDO_tCK = 12;
    DDRSS.lpddr4.config_dram2_tSDO_ns = 20;
    DDRSS.lpddr4.config_dram2_tRC_tCK = "Auto Calc: tRAS + tRP";
    DDRSS.lpddr4.config_dram2_tRC_ns = "";
    DDRSS.lpddr4.config_dram2_tSR_tCK = 3;
    DDRSS.lpddr4.config_dram2_tSR_ns = 15;
    DDRSS.lpddr4.config_dram2_tXSR_tCK = 2;
    DDRSS.lpddr4.config_dram2_tXSR_ns = 387.5;
    DDRSS.lpddr4.config_dram2_tCCD_tCK = 8;
    DDRSS.lpddr4.config_dram2_tCCD_ns = "";
    DDRSS.lpddr4.config_dram2_tCCDMW_tCK = 32;
    DDRSS.lpddr4.config_dram2_tCCDMW_ns = "";
    DDRSS.lpddr4.config_dram2_tRTP_tCK = 8;
    DDRSS.lpddr4.config_dram2_tRTP_ns = 7.5;
    DDRSS.lpddr4.config_dram2_tRCD_tCK = 4;
    DDRSS.lpddr4.config_dram2_tRCD_ns = 19.875;
    DDRSS.lpddr4.config_dram2_tRPpb_tCK = 4;
    DDRSS.lpddr4.config_dram2_tRPpb_ns = 19.875;
    DDRSS.lpddr4.config_dram2_tRPab_tCK = 4;
    DDRSS.lpddr4.config_dram2_tRPab_ns = 22.875;
    DDRSS.lpddr4.config_dram2_tRASmin_tCK = 3;
    DDRSS.lpddr4.config_dram2_tRASmin_ns = 43.875;
    DDRSS.lpddr4.config_dram2_tRASmax_tCK = "";
    DDRSS.lpddr4.config_dram2_tRASmax_ns = 35100;
    DDRSS.lpddr4.config_dram2_tWR_tCK = 4;
    DDRSS.lpddr4.config_dram2_tWR_ns = 18;
    DDRSS.lpddr4.config_dram2_tWTR_tCK = 8;
    DDRSS.lpddr4.config_dram2_tWTR_ns = 10;
    DDRSS.lpddr4.config_dram2_tRRD_tCK = 4;
    DDRSS.lpddr4.config_dram2_tRRD_ns = 9.375;
    DDRSS.lpddr4.config_dram2_tPPD_tCK = 4;
    DDRSS.lpddr4.config_dram2_tPPD_ns = "";
    DDRSS.lpddr4.config_dram2_tFAW_tCK = "";
    DDRSS.lpddr4.config_dram2_tFAW_ns = 30;
    DDRSS.lpddr4.config_dram2_tESCKE_tCK = 3;
    DDRSS.lpddr4.config_dram2_tESCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram2_tDStrain_tCK = "";
    DDRSS.lpddr4.config_dram2_tDStrain_ns = 2;
    DDRSS.lpddr4.config_dram2_tADR_tCK = "";
    DDRSS.lpddr4.config_dram2_tADR_ns = 20;
    DDRSS.lpddr4.config_dram2_tCAENT_tCK = "";
    DDRSS.lpddr4.config_dram2_tCAENT_ns = 250;
    DDRSS.lpddr4.config_dram2_tVREFcalong_tCK = "";
    DDRSS.lpddr4.config_dram2_tVREFcalong_ns = 250;
    DDRSS.lpddr4.config_dram2_tVREFcashort_tCK = "";
    DDRSS.lpddr4.config_dram2_tVREFcashort_ns = 80;
    DDRSS.lpddr4.config_dram2_tCKEHDQS_tCK = "";
    DDRSS.lpddr4.config_dram2_tCKEHDQS_ns = 10;
    DDRSS.lpddr4.config_dram2_tMRZ_tCK = "";
    DDRSS.lpddr4.config_dram2_tMRZ_ns = 1.5;
    DDRSS.lpddr4.config_dram2_tODTonMIN_tCK = "";
    DDRSS.lpddr4.config_dram2_tODTonMIN_ns = 1.5;
    DDRSS.lpddr4.config_dram2_tODTonMAX_tCK = "";
    DDRSS.lpddr4.config_dram2_tODTonMAX_ns = 3.5;
    DDRSS.lpddr4.config_dram2_tODToffMIN_tCK = "";
    DDRSS.lpddr4.config_dram2_tODToffMIN_ns = 1.5;
    DDRSS.lpddr4.config_dram2_tODToffMAX_tCK = "";
    DDRSS.lpddr4.config_dram2_tODToffMAX_ns = 3.5;
    DDRSS.lpddr4.config_dram2_tTSI_tCK = "";
    DDRSS.lpddr4.config_dram2_tTSI_ns = 32000000;
    DDRSS.lpddr4.config_dram2_TempMargin_tCK = "";
    DDRSS.lpddr4.config_dram2_TempMargin_ns = 2;
    DDRSS.lpddr4.config_ddr2_io_cell_mode_dl0 = "Range 0";
    DDRSS.lpddr4.config_ddr2_io_cell_vrefsel_dl0 = 16.7;
    DDRSS.lpddr4.config_ddr2_io_cell_enslicen_drv_dl0_dq = "40 Ohm";
    DDRSS.lpddr4.config_ddr2_io_cell_enslicen_drv_dl0_dqs = "40 Ohm";
    DDRSS.lpddr4.config_ddr2_io_cell_enslicen_drv_ac = "40 Ohm";
    DDRSS.lpddr4.config_ddr2_io_cell_enslicen_drv_cs = "80 Ohm";
    DDRSS.lpddr4.config_ddr2_io_cell_enslicen_odt_dl0_dq = "40 Ohm";
    DDRSS.lpddr4.config_ddr2_io_cell_enslicen_odt_dl0_dqs = "40 Ohm";
    DDRSS.lpddr4.config_dram2_mr14_vr_dq_FS0 = "Range 0";
    DDRSS.lpddr4.config_dram2_mr14_vref_dq_FS0 = 10;
    DDRSS.lpddr4.config_dram2_mr12_vr_ca_FS0 = "Range 0";
    DDRSS.lpddr4.config_dram2_mr12_vref_ca_FS0 = 10;
    DDRSS.lpddr4.config_dram2_mr11_ca_odt_FS0 = "Disable";
    DDRSS.lpddr4.config_dram2_mr11_dq_odt_FS0 = "Disable";
    DDRSS.lpddr4.config_dram2_mr14_vr_dq_FS2 = "Range 0";
    DDRSS.lpddr4.config_dram2_mr14_vref_dq_FS2 = 16;
    DDRSS.lpddr4.config_dram2_mr12_vr_ca_FS2 = "Range 0";
    DDRSS.lpddr4.config_dram2_mr12_vref_ca_FS2 = 25.6;
    DDRSS.lpddr4.config_dram2_mr11_ca_odt_FS2 = "RZQ/3";
    DDRSS.lpddr4.config_dram2_mr11_dq_odt_FS2 = "RZQ/6";
    DDRSS.lpddr4.config_dram2_mr3_pdds_FS2 = "RZQ/6";
    DDRSS.lpddr4.config_dram2_mr3_pu_cal_FS2 = "VDDQ / 3";
    DDRSS.lpddr4.config_dram2_mr22_odtd_ca_FS2 = "ODT_CA Bond Pad";
    DDRSS.lpddr4.config_dram2_mr22_odte_ck_FS2 = "Disable";
    DDRSS.lpddr4.config_dram2_mr22_odte_cs_FS2 = "Enable";
    DDRSS.lpddr4.config_dram2_mr22_soc_odt_FS2 = "RZQ/6";
    DDRSS.lpddr4.system_cfg_dram3_width = 32;
    DDRSS.lpddr4.system_cfg_dram3_density = 16;
    DDRSS.lpddr4.system_cfg_dram3_ranks = 2;
    DDRSS.lpddr4.system_cfg_dram3_mr4_poll = "No";
    DDRSS.lpddr4.system_cfg_sys_temp_grad3 = 30;
    DDRSS.lpddr4.config_dram3_mr1_rd_pre_FS2 = "Static";
    DDRSS.lpddr4.config_dram3_mr1_rd_pst_FS2 = "1.5 x tCK";
    DDRSS.lpddr4.config_dram3_mr3_wr_pst_FS2 = "1.5 x tCK";
    DDRSS.lpddr4.config_dram3_mr3_dbi_rd_FS2 = "Disable";
    DDRSS.lpddr4.config_dram3_mr3_dbi_wr_FS2 = "Disable";
    DDRSS.lpddr4.config_dram3_mr2_rl_FS2 = 36;
    DDRSS.lpddr4.config_dram3_mr2_wls_FS2 = "WL set A";
    DDRSS.lpddr4.config_dram3_mr2_wl_FS2 = 18;
    DDRSS.lpddr4.config_dram3_mr1_nWR_FS2 = 40;
    DDRSS.lpddr4.config_dram3_odtlon_FS2 = 8;
    DDRSS.lpddr4.config_dram3_odtloff_FS2 = 28;
    DDRSS.lpddr4.config_dram3_tINIT1_tCK = "";
    DDRSS.lpddr4.config_dram3_tINIT1_ns = 200000;
    DDRSS.lpddr4.config_dram3_tINIT2_tCK = "";
    DDRSS.lpddr4.config_dram3_tINIT2_ns = 10;
    DDRSS.lpddr4.config_dram3_tINIT3_tCK = "";
    DDRSS.lpddr4.config_dram3_tINIT3_ns = 2000000;
    DDRSS.lpddr4.config_dram3_tINIT4_tCK = 5;
    DDRSS.lpddr4.config_dram3_tINIT4_ns = "";
    DDRSS.lpddr4.config_dram3_tINIT5_tCK = "";
    DDRSS.lpddr4.config_dram3_tINIT5_ns = 2000;
    DDRSS.lpddr4.config_dram3_tPW_RESET_tCK = "";
    DDRSS.lpddr4.config_dram3_tPW_RESET_ns = 100;
    DDRSS.lpddr4.config_dram3_tREFIab_tCK = "";
    DDRSS.lpddr4.config_dram3_tREFIab_ns = 3900;
    DDRSS.lpddr4.config_dram3_tREFIpb_tCK = "";
    DDRSS.lpddr4.config_dram3_tREFIpb_ns = 488;
    DDRSS.lpddr4.config_dram3_tRFCab_tCK = "";
    DDRSS.lpddr4.config_dram3_tRFCab_ns = 380;
    DDRSS.lpddr4.config_dram3_tRFCpb_tCK = "";
    DDRSS.lpddr4.config_dram3_tRFCpb_ns = 190;
    DDRSS.lpddr4.config_dram3_tVRCG_ENABLE_tCK = "";
    DDRSS.lpddr4.config_dram3_tVRCG_ENABLE_ns = 200;
    DDRSS.lpddr4.config_dram3_tVRCG_DISABLE_tCK = "";
    DDRSS.lpddr4.config_dram3_tVRCG_DISABLE_ns = 100;
    DDRSS.lpddr4.config_dram3_tOSCO_tCK = 8;
    DDRSS.lpddr4.config_dram3_tOSCO_ns = 40;
    DDRSS.lpddr4.config_dram3_tZQCAL_tCK = "";
    DDRSS.lpddr4.config_dram3_tZQCAL_ns = 1000;
    DDRSS.lpddr4.config_dram3_tZQLAT_tCK = 8;
    DDRSS.lpddr4.config_dram3_tZQLAT_ns = 30;
    DDRSS.lpddr4.config_dram3_tZQRESET_tCK = 3;
    DDRSS.lpddr4.config_dram3_tZQRESET_ns = 50;
    DDRSS.lpddr4.config_dram3_tFClong_tCK = "";
    DDRSS.lpddr4.config_dram3_tFClong_ns = 250;
    DDRSS.lpddr4.config_dram3_tCKFSPE_tCK = 4;
    DDRSS.lpddr4.config_dram3_tCKFSPE_ns = 7.5;
    DDRSS.lpddr4.config_dram3_tCKFSPX_tCK = 4;
    DDRSS.lpddr4.config_dram3_tCKFSPX_ns = 7.5;
    DDRSS.lpddr4.config_dram3_tDQSCKmin_tCK = "";
    DDRSS.lpddr4.config_dram3_tDQSCKmin_ns = 1.5;
    DDRSS.lpddr4.config_dram3_tDQSCKmax_tCK = "";
    DDRSS.lpddr4.config_dram3_tDQSCKmax_ns = 3.6;
    DDRSS.lpddr4.config_dram3_tCKE_tCK = 4;
    DDRSS.lpddr4.config_dram3_tCKE_ns = 7.5;
    DDRSS.lpddr4.config_dram3_tCMDCKE_tCK = 3;
    DDRSS.lpddr4.config_dram3_tCMDCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram3_tCKELCK_tCK = 5;
    DDRSS.lpddr4.config_dram3_tCKELCK_ns = 5;
    DDRSS.lpddr4.config_dram3_tCSCKE_tCK = "";
    DDRSS.lpddr4.config_dram3_tCSCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram3_tCKELCS_tCK = 5;
    DDRSS.lpddr4.config_dram3_tCKELCS_ns = 5;
    DDRSS.lpddr4.config_dram3_tCKCKEH_tCK = 3;
    DDRSS.lpddr4.config_dram3_tCKCKEH_ns = 1.75;
    DDRSS.lpddr4.config_dram3_tXP_tCK = 5;
    DDRSS.lpddr4.config_dram3_tXP_ns = 7.5;
    DDRSS.lpddr4.config_dram3_tCSCKEH_tCK = "";
    DDRSS.lpddr4.config_dram3_tCSCKEH_ns = 1.75;
    DDRSS.lpddr4.config_dram3_tCKEHCS_tCK = 5;
    DDRSS.lpddr4.config_dram3_tCKEHCS_ns = 7.5;
    DDRSS.lpddr4.config_dram3_tMRWCKEL_tCK = 10;
    DDRSS.lpddr4.config_dram3_tMRWCKEL_ns = 14;
    DDRSS.lpddr4.config_dram3_tZQCKE_tCK = 3;
    DDRSS.lpddr4.config_dram3_tZQCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram3_tMRW_tCK = 10;
    DDRSS.lpddr4.config_dram3_tMRW_ns = 10;
    DDRSS.lpddr4.config_dram3_tMRD_tCK = 10;
    DDRSS.lpddr4.config_dram3_tMRD_ns = 14;
    DDRSS.lpddr4.config_dram3_tMRR_tCK = 8;
    DDRSS.lpddr4.config_dram3_tMRR_ns = "";
    DDRSS.lpddr4.config_dram3_tMRRI_tCK = 3;
    DDRSS.lpddr4.config_dram3_tMRRI_ns = "";
    DDRSS.lpddr4.config_dram3_tSDO_tCK = 12;
    DDRSS.lpddr4.config_dram3_tSDO_ns = 20;
    DDRSS.lpddr4.config_dram3_tRC_tCK = "Auto Calc: tRAS + tRP";
    DDRSS.lpddr4.config_dram3_tRC_ns = "";
    DDRSS.lpddr4.config_dram3_tSR_tCK = 3;
    DDRSS.lpddr4.config_dram3_tSR_ns = 15;
    DDRSS.lpddr4.config_dram3_tXSR_tCK = 2;
    DDRSS.lpddr4.config_dram3_tXSR_ns = 387.5;
    DDRSS.lpddr4.config_dram3_tCCD_tCK = 8;
    DDRSS.lpddr4.config_dram3_tCCD_ns = "";
    DDRSS.lpddr4.config_dram3_tCCDMW_tCK = 32;
    DDRSS.lpddr4.config_dram3_tCCDMW_ns = "";
    DDRSS.lpddr4.config_dram3_tRTP_tCK = 8;
    DDRSS.lpddr4.config_dram3_tRTP_ns = 7.5;
    DDRSS.lpddr4.config_dram3_tRCD_tCK = 4;
    DDRSS.lpddr4.config_dram3_tRCD_ns = 19.875;
    DDRSS.lpddr4.config_dram3_tRPpb_tCK = 4;
    DDRSS.lpddr4.config_dram3_tRPpb_ns = 19.875;
    DDRSS.lpddr4.config_dram3_tRPab_tCK = 4;
    DDRSS.lpddr4.config_dram3_tRPab_ns = 22.875;
    DDRSS.lpddr4.config_dram3_tRASmin_tCK = 3;
    DDRSS.lpddr4.config_dram3_tRASmin_ns = 43.875;
    DDRSS.lpddr4.config_dram3_tRASmax_tCK = "";
    DDRSS.lpddr4.config_dram3_tRASmax_ns = 35100;
    DDRSS.lpddr4.config_dram3_tWR_tCK = 4;
    DDRSS.lpddr4.config_dram3_tWR_ns = 18;
    DDRSS.lpddr4.config_dram3_tWTR_tCK = 8;
    DDRSS.lpddr4.config_dram3_tWTR_ns = 10;
    DDRSS.lpddr4.config_dram3_tRRD_tCK = 4;
    DDRSS.lpddr4.config_dram3_tRRD_ns = 9.375;
    DDRSS.lpddr4.config_dram3_tPPD_tCK = 4;
    DDRSS.lpddr4.config_dram3_tPPD_ns = "";
    DDRSS.lpddr4.config_dram3_tFAW_tCK = "";
    DDRSS.lpddr4.config_dram3_tFAW_ns = 30;
    DDRSS.lpddr4.config_dram3_tESCKE_tCK = 3;
    DDRSS.lpddr4.config_dram3_tESCKE_ns = 1.75;
    DDRSS.lpddr4.config_dram3_tDStrain_tCK = "";
    DDRSS.lpddr4.config_dram3_tDStrain_ns = 2;
    DDRSS.lpddr4.config_dram3_tADR_tCK = "";
    DDRSS.lpddr4.config_dram3_tADR_ns = 20;
    DDRSS.lpddr4.config_dram3_tCAENT_tCK = "";
    DDRSS.lpddr4.config_dram3_tCAENT_ns = 250;
    DDRSS.lpddr4.config_dram3_tVREFcalong_tCK = "";
    DDRSS.lpddr4.config_dram3_tVREFcalong_ns = 250;
    DDRSS.lpddr4.config_dram3_tVREFcashort_tCK = "";
    DDRSS.lpddr4.config_dram3_tVREFcashort_ns = 80;
    DDRSS.lpddr4.config_dram3_tCKEHDQS_tCK = "";
    DDRSS.lpddr4.config_dram3_tCKEHDQS_ns = 10;
    DDRSS.lpddr4.config_dram3_tMRZ_tCK = "";
    DDRSS.lpddr4.config_dram3_tMRZ_ns = 1.5;
    DDRSS.lpddr4.config_dram3_tODTonMIN_tCK = "";
    DDRSS.lpddr4.config_dram3_tODTonMIN_ns = 1.5;
    DDRSS.lpddr4.config_dram3_tODTonMAX_tCK = "";
    DDRSS.lpddr4.config_dram3_tODTonMAX_ns = 3.5;
    DDRSS.lpddr4.config_dram3_tODToffMIN_tCK = "";
    DDRSS.lpddr4.config_dram3_tODToffMIN_ns = 1.5;
    DDRSS.lpddr4.config_dram3_tODToffMAX_tCK = "";
    DDRSS.lpddr4.config_dram3_tODToffMAX_ns = 3.5;
    DDRSS.lpddr4.config_dram3_tTSI_tCK = "";
    DDRSS.lpddr4.config_dram3_tTSI_ns = 32000000;
    DDRSS.lpddr4.config_dram3_TempMargin_tCK = "";
    DDRSS.lpddr4.config_dram3_TempMargin_ns = 2;
    DDRSS.lpddr4.config_ddr3_io_cell_mode_dl0 = "Range 0";
    DDRSS.lpddr4.config_ddr3_io_cell_vrefsel_dl0 = 16.7;
    DDRSS.lpddr4.config_ddr3_io_cell_enslicen_drv_dl0_dq = "40 Ohm";
    DDRSS.lpddr4.config_ddr3_io_cell_enslicen_drv_dl0_dqs = "40 Ohm";
    DDRSS.lpddr4.config_ddr3_io_cell_enslicen_drv_ac = "40 Ohm";
    DDRSS.lpddr4.config_ddr3_io_cell_enslicen_drv_cs = "80 Ohm";
    DDRSS.lpddr4.config_ddr3_io_cell_enslicen_odt_dl0_dq = "40 Ohm";
    DDRSS.lpddr4.config_ddr3_io_cell_enslicen_odt_dl0_dqs = "40 Ohm";
    DDRSS.lpddr4.config_dram3_mr14_vr_dq_FS0 = "Range 0";
    DDRSS.lpddr4.config_dram3_mr14_vref_dq_FS0 = 10;
    DDRSS.lpddr4.config_dram3_mr12_vr_ca_FS0 = "Range 0";
    DDRSS.lpddr4.config_dram3_mr12_vref_ca_FS0 = 10;
    DDRSS.lpddr4.config_dram3_mr11_ca_odt_FS0 = "Disable";
    DDRSS.lpddr4.config_dram3_mr11_dq_odt_FS0 = "Disable";
    DDRSS.lpddr4.config_dram3_mr14_vr_dq_FS2 = "Range 0";
    DDRSS.lpddr4.config_dram3_mr14_vref_dq_FS2 = 16;
    DDRSS.lpddr4.config_dram3_mr12_vr_ca_FS2 = "Range 0";
    DDRSS.lpddr4.config_dram3_mr12_vref_ca_FS2 = 25.6;
    DDRSS.lpddr4.config_dram3_mr11_ca_odt_FS2 = "RZQ/3";
    DDRSS.lpddr4.config_dram3_mr11_dq_odt_FS2 = "RZQ/6";
    DDRSS.lpddr4.config_dram3_mr3_pdds_FS2 = "RZQ/6";
    DDRSS.lpddr4.config_dram3_mr3_pu_cal_FS2 = "VDDQ / 3";
    DDRSS.lpddr4.config_dram3_mr22_odtd_ca_FS2 = "ODT_CA Bond Pad";
    DDRSS.lpddr4.config_dram3_mr22_odte_ck_FS2 = "Disable";
    DDRSS.lpddr4.config_dram3_mr22_odte_cs_FS2 = "Enable";
    DDRSS.lpddr4.config_dram3_mr22_soc_odt_FS2 = "RZQ/6";

  • 0 in reply to Novasky Yao
    TI__Mastermind 38660 points

    DDR Density input parameter should be 4Gb, not 16Gb, as you have total 8Gb (1GB), which is split across two channels (or 4Gb per channel) and the input parameter is asking for density per channel per rank. 

    However, I don't think that is what is causing your issue.

    Can you please run the attached binary and provide the output back to TI? The binary must be loaded / executed through CCS to the R5 core. Output will be displayed in the CCS console window.

    5466.tda4x_lp4_debug2.zip

    Thanks,
    Kevin