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AM6442: How to Optimize the Number of Ferrites in the AM6442

Part Number: AM6442
Other Parts Discussed in Thread: SK-AM62-LP, AM623, AM625

Tool/software:

Hello,

I am designing a board to evaluate the many features of the AM6442. I am using the EVM and StarterKit as references for my design, but I am encountering difficulties due to the large number of ferrites in the power circuit of the AM6442.

I referred to the following URL, which suggests optimizing the number of ferrites by referring to the SK-AM62-LP:

[FAQ] AM625 / AM623 Custom board hardware design – Ferrite (power supply filter) recommendations for SoC supply rails
e2e.ti.com/.../faq-am625-am623-custom-board-hardware-design-ferrite-power-supply-filter-recommendations-for-soc-supply-rails

After reviewing the above URL, I managed to reduce the number of ferrites from 10 to 6. Below are the details of the changes made. Could you please advise if it is possible to reduce the number further?

The number of ferrites for VDDS_OSC has increased. Are these necessary?
The ferrite for VDDAR_0P85_USB0 has been removed. Is it unnecessary?
The SK-AM62-LP does not have ferrites for VDDA_ADC, VDD_DLL_MMC0, and VDDAR_0P85_SERDES0. Can these ferrites be removed?

Before: 10 ferrites
VDDA_CORE -> Ferrite -> VDDAR_0P85_SERDES0 -> [AM64] VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C
VDDA_CORE -> Ferrite -> VDDAR_0P85_USB0 ----> [AM64] VDDA_0P85_USB0
VDDA_CORE -> Ferrite -> VDD_DLL_MMC0 -------> [AM64] VDD_DLL_MMC0
VDDA_1V8 --> Ferrite -> VDDA_1V8_SERDES ----> [AM64] VDDA_1P8_SERDES0
VDDA_1V8 --> Ferrite -> VDDA_ADC -----------> [AM64] VDDA_ADC, ADC0_REFP
VDDA_1V8 --> Ferrite -> VDDA_1V8_USB0 ------> [AM64] VDDA_1P8_USB0
VDDA_1V8 -----------------------------------> [AM64] VDDS_OSC
VDDA_1V8 -----------------------------------> [AM64] VDDA_TEMP0
VDDA_1V8 -----------------------------------> [AM64] VDDA_TEMP1
VDDA_1V8 --> Ferrite -> VDDA_PLL0 ----------> [AM64] VDDA_PLL0
VDDA_1V8 --> Ferrite -> VDDA_PLL1 ----------> [AM64] VDDA_PLL1
VDDA_1V8 --> Ferrite -> VDDA_PLL2 ----------> [AM64] VDDA_PLL2
VDDA_1V8 --> Ferrite -> VDDA_1V8_MCU -------> [AM64] VDDA_MCU

After: 6 ferrites
VDDA_CORE -> Ferrite -> VDDAR_0P85_SERDES0 -> [AM64] VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C
VDDA_CORE ----------------------------------> [AM64] VDDA_0P85_USB0
VDDA_CORE -> Ferrite -> VDD_DLL_MMC0 -------> [AM64] VDD_DLL_MMC0
VDDA_1V8 --> Ferrite -> VDDA_1V8_SERDES ----> [AM64] VDDA_1P8_SERDES0
VDDA_1V8 --> Ferrite -> VDDA_ADC -----------> [AM64] VDDA_ADC, ADC0_REFP
VDDA_1V8 -----------------------------------> [AM64] VDDA_1P8_USB0
VDDA_1V8 --> Ferrite -> VDDA_1V8_FB_OSC ----> [AM64] VDDS_OSC
VDDA_1V8 --> Ferrite -> VDDA_1V8_FB1 -------> [AM64] VDDA_TEMP[0-1], VDDA_PLL[0-2], VDDA_MCU

  • Hello TK0312, 

    Thank you for the query.

    Can you put the changes on a block diagram for ease of review.

    You could refer SK-AM62-LP to further optimize as required.

    Regards,

    Sreenivasa

  • Sreenivasa - caution here; especially on the lower voltages. EMI/EMC remediation after removing some ferrites could be an issue. Keep in mind that the 7th harmonic emission of a 1GHz clock could be a problem.

    Jim.

  • Hello Kallikuppa,

    Thank you for your response.

    I am providing a block diagram.

    The power pins highlighted in orange indicate where the ferrite connections have been modified.

    Please help me optimize the number of ferrites.

    We are using the "BLM18PG121SN1" ferrite here.

    We chose this ferrite because it was used in other products, but other Murata ferrites would also be acceptable.

    Could you please advise on any considerations when selecting ferrites?

  • Hello TK0312, 

    Thank you.

    I am not sure if you have had a chance to review SK-AM62-LP. 

    The Only other optimization could be combining the VDDA supplies.

    As Jim mentioned, the optimization needs to be tested under the specific implementation to confirm they work.

    If the performance is a concern, during the initial board design you could provision for ferrites, replace them with 0R, test and optimize.

    Regards,

    Sreenivasa


  • Hello Kallikuppa,

    Could you please confirm if there are no major issues with the changes I proposed in the "After" section? For example, was it a good decision to remove the ferrites for VDDAR_0P85_USB0 and VDDA_1P8_USB0?

    Regarding your advice to combine the VDDA supplies, do you have any specific guidelines? For instance, should the ferrite for SERDES0 be retained while considering the removal of the ferrite for ADC?

    The reason I want to reduce the number of ferrites is not to cut costs, but to simplify the wiring by reducing the number of power supply types, which can be obstructive.

    Thank you for your assistance.

    Best regards,

    TK0312

  • Hello TK0312

    Thank you.

    It is always recommended to connect the peripheral core supplies and the VDDA supplies through ferrites.

    Ferrites can be individual or grouped as shown in different SKs.

    All the required simulations and testing is expected to be performed to confirm the suitability of the specific  configuration,

    Regards,

    Sreenivasa

  • You really do not want noise from a VDDA powered analog section on the die getting coupled onto a physically different VDD powered analog section on the same die.

  • Hello Kallikuppa and Jim,

    Thank you, your advice has been very helpful in improving my understanding. I now understand that it is very problematic for the VDDA and VDD supplies to be directly connected.

    What you are saying is that it is not a good idea to remove the ferrites for VDDAR_0P85_USB0 and VDDA_1P8_USB0. However, I understand that it is acceptable to share ferrites used elsewhere.

    I have created a new block diagram. Please let me know if you notice any issues with this diagram.

    (1) moved to serdes ferrite (2) moved to VDDA ferrite (3) moved to serdes ferrite (4) no ferrite in EVM schematic

    Are there any issues with the points (1) to (4) noted in the diagram?

  • Keep in mind that VDDCORE (both on the very lowest of the voltages used in the core) may STILL have 1GHz harmonics with 1 GHz synthesized clock rate.

    I'll defer to what Sreenivasa officially responds.

  • Hello TK0312

    Thank you.

    You might want to have an option to separate the VDDA0..2 PLL just in case and optimize later.

    Regards,

    Sreenivasa

  • Hello Sreenivasa,

    Your comments are very clear and helpful. I am not opposed to adding ferrites again, as my goal is not to reduce components forcibly.

    Is it optimal to isolate the VDDA_PLL[2-0] power supply with additional ferrites? If there are any other pins that should be moved together with VDDA_PLL, please let me know.

    Below is the current optimal power supply configuration diagram.

    Thank you for your assistance.

    Best regards,

    TK0312

  • Hello TK0312

    Thank you.

    I do not have additional inputs.

    Regards,

    Sreenivasa

  • Hello Sreenivasa,

    Thank you very much for your assistance. Your guidance has been invaluable, and I am pleased to inform you that we have achieved an optimal power supply configuration for the AM6442.

    Best regards,

    TK0312

  • Hello TK0312

    Thank you for the note, appreciated.

    Regards,

    Sreenivasa