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TDA4VM: CPSW2G: Priority (0 - 7) Maximum Transmit Packet Length Register usage details needed

Hasan Aarzoo
Intellectual 495 points
Part Number: TDA4VM


Tool/software:

Hi TI,

Hope you are doing well.

I have a few questions about the usage of Priority Maximum Transmit Packet Length Register (e.g. CPSW_TX_PRI0_MAXLEN_REG). I am using CPSW2G. The questions are as follows:

  1. Why is the reset value of CPSW_TX_PRI0_MAXLEN_REG is 0x7E8 not 0x5EE, while Maximum Receive Packet Length Register (CPSW_P0_RX_MAXLEN_REG) is 0x5EE?
    Is it reset value of both registers (CPSW_TX_PRI0_MAXLEN_REG  and CPSW_P0_RX_MAXLEN_REG) configured different intentional by TI? If yes, why?

  2. Why we have 8 Priority Maximum Transmit Packet Length Register? What are they used for?

Looking forward to hearing back from you.

Best Regards,
Hasan Aarzoo

  • +1
    TI__Mastermind 41190 points

    Hi Hasan,

    Hasan Aarzoo said:
    1. Why we have 8 Priority Maximum Transmit Packet Length Register? What are they used for?

    So these are per priority maxlength register. In some case, you might not want to transmit bigger packets on some higher priority. These registers will help enforce that.

    Hasan Aarzoo said:
    Is it reset value of both registers (CPSW_TX_PRI0_MAXLEN_REG  and CPSW_P0_RX_MAXLEN_REG) configured different intentional by TI? If yes, why?

    I cannot be sure about this. But as the Rx registers have to be configured based on the MTU size, they would have been tailored for the standard mtu of 1500. While the CPSW_TX_PRIn_MAXLEN_REG are not controlled by the change in MTU, and hence are kept at hardware maximum.

    Regards,
    Tanmay