TDA4VM-Q1: TDA4VM LPDDR4 sysconfig and impedance matching issues

Also, it looks like the J721e layout is changing the line impedance after the T-split for all the CA pins and CK, but not for the CKE pins.
CKE are kept as wide (lower impedance) traces even after the split.

Is this intentional, or an oversight?

I found an answer to the CKE layout impedance question here, where TI confirms that the CKE is not impedance matched correctly on J721 EVM.
If should be 40 before the T-junction and 80 after (or other impedances with 1:2 ratio)

e2e.ti.com/.../j721s2xsomxevm-lpddr4-layout-and-cke-impedance-track

Anders Kagerin said:

1. First I'd want to make a bug report that the online Sysconfig tool (v0.11.0) does not have the correct settings for Vref.

"VREF Control - DQ VREF" and "VREF Control - CA VREF" both list range 10 - 30, but the DRAM part MT53E1G32D2 lists 15 - 44.9% (for range 0).
After checking the output, it seems like Micron 15% is code 0 (programmed into MR12/14), and Sysconfig 10% is code 0, so I could make a reverse-lookup formula to calculate it.
Using this formula I could set the correct VREF values for my design.

I would suggest replacing the percentages with the raw codes instead, since this seems to be part-dependent.

10% to 30% corresponds to range 0 of LPDDR4.
15% to 44.9% corresponds to range 0 of LPDDR4x, which TDA4VM does not support.

These values are defined by the JEDEC standard, and hypothetically should not be part dependent.

Additionally, VREF is trained during initialization and the values selected by the tool will be over-written. 

Anders Kagerin said:

2. What is the behavior of the CTL ODTs? And how does the "CK/CS ODT Override" setting change this behavior?
I believe this is highly related to Q3 below.

I am not sure I fully understand the question. CK/CS ODT override settings are control bits in MR22 of the LPDDR4 memory. There should be a table in your LPDDR4 datasheet that describes the ODT state of CA, CK, and CS based on the MR11 and MR22 configuration. Table name may be similar to "Command Bus ODT State".

Note that similar to MR12 / MR14, MR22 has a different definition between LPDDR4 and LPDDR4x.

Anders Kagerin said:

but it seems that only one die has ODTca pin connected, the other being disabled.
Is this the behavior that is changed with the "Override" settings?

For dual rank memories, typically there is a single terminating rank. In some cases, you may want to enable the termination when CA is shared but CS/CK are not.

Regards,
Kevin

Hi Kevin,

Thanks for pointing out my obvious mistake regarding LPDDR4 vs the X version. The datasheet I'm looking at defines both X and regular versions, so I mistakenly looked at the wrong information.

Is the Vref setting used for anything before calibration? Or should I just leave it all at the defaults?

To clarify Q2/3. Please tell me if I have misunderstood any of the following:

1. CA nets are shared through the T-junction, and therefore the ODT should always be enabled for both channels.

Internally in our part (MT53E1G32D2) the second die connects ODT_CA to GND, so only one die per channel will enable ODT.

The PCB is always driving ODT_CA to VCCQ for both channels, terminating both ends after the T-junction.
So the effective ODT impedance seen by the SOC will be half of the ODT setting.

This is the corresponding setting:

2. CK is routed and split identically to CA, so it should retain the same/default behavior.

3. CS is not split, therefore the SOC will only see one ODT resistor.

As far as I can determine, this setting enables the ODT termination in the second die (ignoring ODT_CA = GND).

This would mean the the SOC (CS pin) will also see two ODT resistors, but now one per die, instead of one per channel.
The effective ODT impedance seen by the SOC will be half of the ODT setting, just like for CA/CK.

Anders Kagerin said:

The PCB is always driving ODT_CA to VCCQ for both channels, terminating both ends after the T-junction.
So the effective ODT impedance seen by the SOC will be half of the ODT setting.

Yes, that is also my understanding.

Anders Kagerin said:

As far as I can determine, this setting enables the ODT termination in the second die (ignoring ODT_CA = GND).

Yes, it should enable ODT for the rank which would otherwise have ODT_CA = GND.

Anders Kagerin said:

The effective ODT impedance seen by the SOC will be half of the ODT setting, just like for CA/CK.

There is a unique chip select IO per channel and per rank (4x total). Whereas there is only a single CA0 IO signal, that is routed to both channels and both ranks. So while I agree that CA0 would have an effective ODT impedance of half of the ODT setting, I believe the effective ODT of CS will match the programmed ODT setting.

Regards,
Kevin

Ah, of course, this makes sense. So ideally CS should be routed with a higher impedance trace to match the "double" ODT impedance (compared to CS/CK).

The override setting here, simply forces ODT to be enabled for CSN1 nets going to the second die.

Is there a way to get a Shmoo diagram for the DRAM? I think I stumbled across something for this using the JTAG debugger, but I can't find it anymore.
Since I don't have access to a debugger, having a program that could run in the bootloader and print to the serial port would be better for me.

Hi,

Anders Kagerin said:

Since I don't have access to a debugger

To clarify, you do not have JTAG on your board?

Regards,
Kevin

Yes, no JTAG access.