Tool/software:
When running our proprietary OS on TDA4AH/TDA4VH, CPU exception often occurs.
The value of Exception Syndrome Register (ESR) is 0xBF000002, I recognized that the reason of CPU exception is SError.
AArch64 ESR decoder
In the case of SError, the information in the ISS field of ESR register is IMPLEMENTATION DEFINED.
As far as I checked the Technical Reference Manual for Cortex-A72, the contents of the ISS field indicated "Slave error".
ARM Cortex-A72 MPCore Processor Technical Reference Manual r0p3
[Questions]
1) When the "SError" CPU exception occured, is there any IMPLEMENTATION DEFINED information that TDA4AH/TDA4VH records in the ISS field of ESR register?
2) If the answer to 1) is "No", the information in the ISS field is considered to conform to the Cortex-A72 specification(= Slave error occurs).
- Which devices or peripherals does "Slave" refer to?
- Are there any registers that should be checked when investigating the Slave error?
Thanks.
Hello,
Thanks for your question. We are assigning this to our expert.
Regards,
Sarabesh S.