AM4376: TPS65218D0 is use for Powering up AM4376bzdnd30 but the PGOOD is arriving before DCDC2 development.

Hi,

Please read through the following post: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1071334/notice-regarding-processor-sdk-ti-rtos-for-am335x-am437x-omap-l13x-c674x-k2g-devices

Regards,

Vaibhav

I checked the older thread but no similar issue is bugged.

As of now I removed DCDC2 connection to MPU and still the problem is existing , so the problem seems more on PMIC side -TPS65218D0

Ideally , PGood not be High until and unless all rails are up , but for my case it is High Before DCDC2 is stable to 1.1V.

Hi Vinay,

Assuming you have filtered out the following:

Vinaykumar Yadav said:

so the problem seems more on PMIC side -TPS65218D0

I am reassigning this thread. Please expect responses in sometime.

Regards,

Vaibhav

Hi Vinaykumar, 

Are you able to show waveform captures of the power up sequence you are seeing? When is PGOOD going high in respect to DCDC2?
And are you using I2C in your system to read/write to the PMIC at all?

Best Regards, 
Sarah

Channel 1 - DC DC 2
Channel 2 - PGood

We have kept provision for I2c communication between PMIC and Processeor but we are not using it.

We have not moved ahead on these boards since "cccc" itself is not coming.

Regards,

Vinay

Hi Vinay, 

Thank you for the waveform. It appears there is a ~8ms gap between the PGOOD to DCDC2..
There should at least be a 20 ms delay by default between the last power rail (DCDC2)  to PGOOD.

Do you notice this PGOOD coming up 20ms after DCDC6, or DCDC1, or any other outputs?

Are you able to share your schematic here - or over private message/email if privacy is a concern? 
And tell me what rail is being used as the pullup source for PGOOD?

Best Regards, 
Sarah