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AM625: DDR Margin Tool

Lawrence Wong
Genius 15950 points
Part Number: AM625
Other Parts Discussed in Thread: SK-AM62

Tool/software:

Customer decided to first run DDR Margin Tool on the AM62 dev board we have - the "SK-AM62". That way we have a known good result for comparison and just to learn how to use this tool.

 

But they seem to have run into an issue. It seems like the tool is either failing everything or they are doing something wrong. 

 

One of the things they noticed after some investigation is that the tool seems to only be able to work with LPDDR4 and not DDR4. Is this true, or are they just entering a wrong setting somewhere?

 

If the tool can just use LPDDR4 then that seems like it couldn't even run on all TI evm kits, which would be confusing. And just in general the tool seems to only internally mention that it only works for LPDDR4 making it even more confusing.

 

I have attached some of the outputs they see when they try to run this tool on the SK-AM62 EVM. 

 

Fullscreen 0486.MARGIN TOOL OUTPUT.txt Download 
******************************************************************                                                 
  _______     ________     ________   _______ ____   ____  _                                                          
|__   __|   |  ____\ \   / /  ____| |__   __/ __ \ / __ \| |                                                         
    | |      | |__   \ \_/ /| |__       | | | |  | | |  | | |     
    | |      |  __|   \   / |  __|      | | | |  | | |  | | |     
    | |      | |____   | |  | |____     | | | |__| | |__| | |____ 
    |_|      |______|  |_|  |______|    |_|  \____/ \____/|______|

******************************************************************
                     DDRSS "Teye" Tool
                     Version 1.8.0
Jacinto created and Sitara iterated toolset across SoCs and platforms
Tool only supports LPDDR4
Tool expects the MMU/MPU properties for:
        DDR SDRAM region to be WBWA cacheable
        DDR CTRL region to be Device/Strongly-Ordered memory
Tool does not comprehend margins across chip selects and only does current controller set point
******************************************************************
******************************************************************
TEYE_TOOL_START
SOC Type=AM62x
Detecting user configuration and saving important parameters
        DETECTED: DDR Instance is DDRSS0
        DETECTED: DRAM class: 0xa == DDR4
UNDEFINED
ERROR: Only LPDDR4 is supported by this tool
ERROR: Exiting during query to DDR registers!
ERROR: Failed to parse DDR registers before margin analysis!
TEYE_TOOL_DONE

0486.evm_results.txt

4111.evm_results.pdf

  • 0
    TI__Expert 5725 points

    Greetings Lawrence,

    This is correct, the tool currently only supports LPDDR4 as it is used across all Sitara devices, while DDR4 is only on some of them. DDR4 support is not currently planned, but we are looking into it. 

    Sincerely,

    Lucas

  • 0 in reply to Lucas Bowe
    TI__Genius 15950 points

    Hi Lucas,

    Ok, any guidance for customer using DDR4?  What testing options are avaliable to validate the design?

    Regards,

    Lawrence

  • 0 in reply to Lawrence Wong
    TI__Expert 5725 points

    Hey Lawrence,

    We have the DDR board design and layout guidelines here: https://www.ti.com/lit/pdf/sprad06, which should aid in board design and simulations.

    For actual board testing most customers have a validation strategy in mind already, but a basic start would be running an open source memtester overnight (Linux has one built in). More complex validation strategies would be something like running several boards in thermal chambers across varying temperatures, but that's the customer's prerogative to do so.

    Sincerely,

    Lucas