Part Number: DRA821U
Other Parts Discussed in Thread: J7200XSOMXEVM
Tool/software:
Hi Team,
We have designed a custom board based on the J7200XSOMXEVM reference design.
We are developing the software for the custom board with PROCESSOR-SDK-LINUX-RT-J7200 (10.00.07.03).
MCU_CPSW of the custom board has the following configuration.
To enable the MCU_CLKOUT0 clock output, bit 4 of the CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL register (0x40F08010) was set to 1.
However, MCU_CLKOUT0 clock is not output.
[device tree]
&wkup_pmx2 {
...
ethernet_pins_default: ethernet-pins_default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x00, PIN_INPUT, 1) /* (D11) MCU_RGMII1_TX_CTL.MCU_RMII1_CRS_DV */
J721E_WKUP_IOPAD(0x04, PIN_INPUT, 1) /* (A11) MCU_RGMII1_RX_CTL.MCU_RMII1_RX_ER */
J721E_WKUP_IOPAD(0x10, PIN_OUTPUT, 1) /* (B11) MCU_RGMII1_TD1.MCU_RMII1_TXD1 */
J721E_WKUP_IOPAD(0x14, PIN_OUTPUT, 1) /* (D10) MCU_RGMII1_TD0.MCU_RMII1_TXD0 */
J721E_WKUP_IOPAD(0x18, PIN_OUTPUT, 1) /* (A12) MCU_RGMII1_TXC.MCU_RMII1_TX_EN */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (B10) MCU_RGMII1_RXC.MCU_RMII1_REF_CLK */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (B9) MCU_RGMII1_RD1.MCU_RMII1_RXD1 */
J721E_WKUP_IOPAD(0x2c, PIN_INPUT, 1) /* (A9) MCU_RGMII1_RD0.MCU_RMII1_RXD0 */
>;
};
dp83822_mdio_pins_default: dp83822-mdio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (D9) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x30, PIN_INPUT, 0) /* (C9) MCU_MDIO0_MDIO */
>;
};
mcu_clkout_pins_default: mcu-clkout-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x83, PIN_OUTPUT, 6) /* (C16) WKUP_GPIO0_11.MCU_CLKOUT0 */
>;
};
...
};
...
&mcu_cpsw {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <ðernet_pins_default>, <&dp83822_mdio_pins_default>;
};
&davinci_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
rx-internal-delay-ps = <1>;
tx-internal-delay-ps = <1>;
};
};
&cpsw_port1 {
status = "okay";
phy-mode = "rmii";
phy-handle = <&phy0>;
};
...
[CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL]
~# devmem2 0x40F08010 /dev/mem opened. Memory mapped at address 0xffff93904000. Read at address 0x40F08010 (0xffff93904010): 0x00000000 ~# devmem2 0x40F08010 w 0x10 /dev/mem opened. Memory mapped at address 0xffffafc80000. Read at address 0x40F08010 (0xffffafc80010): 0x00000000 Write at address 0x40F08010 (0xffffafc80010): 0x00000010, readback 0x00000010 ~# devmem2 0x40F08010 /dev/mem opened. Memory mapped at address 0xffff9e1f4000. Read at address 0x40F08010 (0xffff9e1f4010): 0x00000010
How can we enable the MCU_CLKOUT0 clock output?
Also, is it possible to set the 4th bit of CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL to 1 in the device tree settings?
Regards,
mizutani
