DRA821U: About WKUP_GPIO0_6

user4852186

Intellectual 340 points

Part Number: DRA821U
Other Parts Discussed in Thread: J7200XSOMXEVM

Tool/software:

Hi Team,

We have designed a custom board based on the J7200XSOMXEVM reference design.

We are developing the software for the custom board with PROCESSOR-SDK-LINUX-RT-J7200 (10.00.07.03).

The custom board is equipped with a 7-segment LED display. The pin configuration is as follows:

	sseg_led_pins_default: sseg-led-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 7) /* (B21) WKUP_GPIO0_3 */
			J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 7) /* (D13) WKUP_GPIO0_4 */
			J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 7) /* (B16) WKUP_GPIO0_5 */
			J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 7) /* (C14) WKUP_GPIO0_6 */
			J721E_WKUP_IOPAD(0x74, PIN_OUTPUT, 7) /* (C18) WKUP_GPIO0_7 */
			J721E_WKUP_IOPAD(0x78, PIN_OUTPUT, 7) /* (C21) WKUP_GPIO0_8 */
			J721E_WKUP_IOPAD(0x7c, PIN_OUTPUT, 7) /* (C19) WKUP_GPIO0_9 */
			J721E_WKUP_IOPAD(0x80, PIN_OUTPUT, 7) /* (C20) WKUP_GPIO0_10 */
		>;
	};

"GPIO Direction Register" is set to output during bootloader(u-boot).

=> gpio status -a
Bank gpio@42110000_:
gpio@42110000_0: input: 0 [ ]
gpio@42110000_1: input: 0 [ ]
gpio@42110000_2: input: 0 [ ]
gpio@42110000_3: output: 0 [ ]
gpio@42110000_4: output: 0 [ ]
gpio@42110000_5: output: 0 [ ]
gpio@42110000_6: output: 0 [ ]
gpio@42110000_7: output: 0 [ ]
gpio@42110000_8: output: 0 [ ]
gpio@42110000_9: output: 0 [ ]
gpio@42110000_10: output: 0 [ ]
...

However, during kernel startup, some LEDs lit up unintentionally. Upon checking the registers, it was found that the "GPIO Direction Register" had been rewritten.

~# devmem2 0x42110010
/dev/mem opened.
Memory mapped at address 0xffffa0f82000.
Read at address  0x42110010 (0xffffa0f82010): 0xFFFFF847

I checked the device tree and there were no pin conflicts.

Are there any other things I should check besides the device tree?

Also, the reference design J7200XSOMXEVM uses WKUP_GPIO0_6 as an input. Does this have any effect?

Regards,

mizutani

9 months ago

0 Keerthy J 9 months ago

TI__Guru**** 165090 points

Hello mizutani,

There are 2 levels to configuring a pin as GPIO:

PADCONFIG level at which the pin has to be configured as PIN_INPUT.
This is a must for GPIO mode. Basically bit18 of the PADCONFIG register has to be set to 1. The mode has to be set to 0x7. Which means:
J721E_WKUP_IOPAD(0x64, PIN_INPUT, 7) /* (B21) WKUP_GPIO0_3 */
J721E_WKUP_IOPAD(0x68, PIN_INPUT, 7) /* (D13) WKUP_GPIO0_4 */
J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 7) /* (B16) WKUP_GPIO0_5 */
J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
J721E_WKUP_IOPAD(0x74, PIN_INPUT, 7) /* (C18) WKUP_GPIO0_7 */
J721E_WKUP_IOPAD(0x78, PIN_INPUT, 7) /* (C21) WKUP_GPIO0_8 */
J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 7) /* (C19) WKUP_GPIO0_9 */
J721E_WKUP_IOPAD(0x80, PIN_INPUT, 7) /* (C20) WKUP_GPIO0_10 */
At the GPIO level you can configure that as output.

- Keerthy

0 user4852186 9 months ago in reply to Keerthy J

Intellectual 340 points

Hi,

We have tried modifying the device tree as follows, but it did not change the result:

	sseg_led_pins_default: sseg-led-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x64, PIN_INPUT, 7) /* (B21) WKUP_GPIO0_3 */
			J721E_WKUP_IOPAD(0x68, PIN_INPUT, 7) /* (D13) WKUP_GPIO0_4 */
			J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 7) /* (B16) WKUP_GPIO0_5 */
			J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
			J721E_WKUP_IOPAD(0x74, PIN_INPUT, 7) /* (C18) WKUP_GPIO0_7 */
			J721E_WKUP_IOPAD(0x78, PIN_INPUT, 7) /* (C21) WKUP_GPIO0_8 */
			J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 7) /* (C19) WKUP_GPIO0_9 */
			J721E_WKUP_IOPAD(0x80, PIN_INPUT, 7) /* (C20) WKUP_GPIO0_10 */
		>;
	};

In U-boot, the "GPIO Direction Register" was 0xFFFFF807, but after the kernel starts, it becomes 0xFFFFF847.

Our requirement is that the "GPIO Direction Register" be persistently set to 0xFFFFF807 after u-boot execution.

However, for some reason, only WKUP_GPIO0_6 changes.

Could you please tell me how to fix this or how to investigate the cause?

Regards,

mizutani

0 Keerthy J 9 months ago in reply to user4852186

TI__Guru**** 165090 points

Hi,

https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts?h=ti-linux-6.6.y#n158

Check on your codebase if you want to remove that.

- Keerthy

0 user4852186 9 months ago in reply to Keerthy J

Intellectual 340 points

Hi,

We have confirmed that there is no conflict with WKUP_GPIO0_6(C14).

We have attached the build information(dtb.dts.tmp) for the device tree for the custom board, so please check it.

# 0 "arch/arm64/boot/dts/company_name/custom-board.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/company_name/custom-board.dts"


/dts-v1/;

# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 6 "arch/arm64/boot/dts/company_name/custom-board.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
# 7 "arch/arm64/boot/dts/company_name/custom-board.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/ti,sci_pm_domain.h" 1
# 8 "arch/arm64/boot/dts/company_name/custom-board.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 9 "arch/arm64/boot/dts/company_name/custom-board.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 10 "arch/arm64/boot/dts/company_name/custom-board.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/net/ti-dp83867.h" 1
# 11 "arch/arm64/boot/dts/company_name/custom-board.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/phy/phy.h" 1
# 12 "arch/arm64/boot/dts/company_name/custom-board.dts" 2

# 1 "arch/arm64/boot/dts/company_name/../ti/k3-pinctrl.h" 1
# 14 "arch/arm64/boot/dts/company_name/custom-board.dts" 2
# 1 "arch/arm64/boot/dts/company_name/../ti/k3-serdes.h" 1
# 15 "arch/arm64/boot/dts/company_name/custom-board.dts" 2

/ {
 model = "company_name custom-board";
 compatible = "ti,j7200";
 interrupt-parent = <&gic500>;
 #address-cells = <2>;
 #size-cells = <2>;

 aliases {
  serial1 = &mcu_uart0;
  serial2 = &main_uart0;
  serial3 = &main_uart1;
  mmc0 = &main_sdhci0;
  mmc1 = &main_sdhci1;
  ethernet0 = &cpsw_port1;
  ethernet1 = &cpsw0_port2;
  ethernet2 = &cpsw0_port3;
 };

 chosen {
  stdout-path = "serial2:115200n8";
 };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;
  cpu-map {
   cluster0: cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };
   };

  };

  cpu0: cpu@0 {
   compatible = "arm,cortex-a72";
   reg = <0x000>;
   device_type = "cpu";
   enable-method = "psci";
   i-cache-size = <0xc000>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <0x8000>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&L2_0>;
  };

  cpu1: cpu@1 {
   compatible = "arm,cortex-a72";
   reg = <0x001>;
   device_type = "cpu";
   enable-method = "psci";
   i-cache-size = <0xc000>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <0x8000>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&L2_0>;
  };
 };

 L2_0: l2-cache0 {
  compatible = "cache";
  cache-level = <2>;
  cache-unified;
  cache-size = <0x100000>;
  cache-line-size = <64>;
  cache-sets = <1024>;
  next-level-cache = <&msmc_l3>;
 };

 msmc_l3: l3-cache0 {
  compatible = "cache";
  cache-level = <3>;
  cache-unified;
 };

 firmware {
  optee {
   compatible = "linaro,optee-tz";
   method = "smc";
  };

  psci: psci {
   compatible = "arm,psci-1.0";
   method = "smc";
  };
 };

 a72_timer0: timer-cl0-cpu0 {
  compatible = "arm,armv8-timer";
  interrupts = <1 13 8>,
        <1 14 8>,
        <1 11 8>,
        <1 10 8>;
 };

 pmu: pmu {
  compatible = "arm,cortex-a72-pmu";
  interrupts = <1 7 4>;
 };

 cbass_main: bus@100000 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>,
    <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>,
    <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>,
    <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>,
    <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>,
    <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>,
    <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>,
    <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>,
    <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>,
    <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>,


    <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
    <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
    <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
    <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
    <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
    <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
    <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
    <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
    <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
    <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
    <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
    <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
    <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;

  cbass_mcu_wakeup: bus@28380000 {
   compatible = "simple-bus";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
     <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
     <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
     <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
     <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
     <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
     <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
     <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
     <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
     <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
     <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
     <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
     <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
  };
 };

 thermal_zones: thermal-zones {
  mcu_thermal: mcu-thermal {
   polling-delay-passive = <250>;
   polling-delay = <500>;
   thermal-sensors = <&wkup_vtm0 0>;

   trips {
    wkup_crit: wkup-crit {
     temperature = <115000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };
  };

  mpu_thermal: mpu-thermal {
   polling-delay-passive = <250>;
   polling-delay = <500>;
   thermal-sensors = <&wkup_vtm0 1>;

   trips {
    mpu_crit: mpu-crit {
     temperature = <115000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };
  };

  main_thermal: main-thermal {
   polling-delay-passive = <250>;
   polling-delay = <500>;
   thermal-sensors = <&wkup_vtm0 2>;

   trips {
    c7x_crit: c7x-crit {
     temperature = <115000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };
  };
 };

 memory@80000000 {
  device_type = "memory";
  bootph-all;

  reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
        <0x00000008 0x80000000 0x00000000 0x80000000>;
 };

 reserved_memory: reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  secure_ddr: optee@9e800000 {
   reg = <0x00 0x9e800000 0x00 0x01800000>;
   alignment = <0x1000>;
   no-map;
  };
 };

 evm_12v0: fixedregulator-evm12v0 {

  compatible = "regulator-fixed";
  regulator-name = "evm_12v0";
  regulator-min-microvolt = <12000000>;
  regulator-max-microvolt = <12000000>;
  regulator-always-on;
  regulator-boot-on;
 };

 vsys_3v3: fixedregulator-vsys3v3 {

  compatible = "regulator-fixed";
  regulator-name = "vsys_3v3";
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
  vin-supply = <&evm_12v0>;
  regulator-always-on;
  regulator-boot-on;
 };

 vsys_5v0: fixedregulator-vsys5v0 {

  compatible = "regulator-fixed";
  regulator-name = "vsys_5v0";
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  vin-supply = <&evm_12v0>;
  regulator-always-on;
  regulator-boot-on;
 };

 vdd_mmc1: fixedregulator-sd {

  compatible = "regulator-fixed";
  regulator-name = "vdd_mmc1";
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
  regulator-boot-on;
  enable-active-high;
  vin-supply = <&vsys_3v3>;
 };

 vdd_sd_dv: gpio-regulator-TLV71033 {

  compatible = "regulator-gpio";
  regulator-name = "tlv71033";
  pinctrl-names = "default";
  pinctrl-0 = <&vdd_sd_dv_pins_default>;
  regulator-min-microvolt = <1800000>;
  regulator-max-microvolt = <3300000>;
  regulator-boot-on;
  vin-supply = <&vsys_5v0>;
  gpios = <&main_gpio0 55 0>;
  states = <1800000 0x0>,
    <3300000 0x1>;
 };

 leds {
  compatible = "gpio-leds";
  pinctrl-names = "default";
  pinctrl-0 = <&emmc_access_mon_pins_default>;

  led0 {
   label = "7seg:DP:mmc1";
   gpios = <&wkup_gpio0 10 1>;
   linux,default-trigger = "mmc1";
   default-state = "off";
  };
 };
};

# 1 "arch/arm64/boot/dts/company_name/../ti/k3-j7200-main.dtsi" 1







/ {
 serdes_refclk: serdes-refclk {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };
};

&cbass_main {
 msmc_ram: sram@70000000 {
  compatible = "mmio-sram";
  reg = <0x00 0x70000000 0x00 0x100000>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x00 0x00 0x70000000 0x100000>;

  atf-sram@0 {
   reg = <0x00 0x20000>;
  };
 };

 scm_conf: scm-conf@100000 {
  compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  reg = <0x00 0x00100000 0x00 0x1c000>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x00 0x00 0x00100000 0x1c000>;

  serdes_ln_ctrl: mux-controller@4080 {
   compatible = "reg-mux";
   reg = <0x4080 0x20>;
   #mux-control-cells = <1>;
   mux-reg-masks = <0x0 0x3>, <0x4 0x3>,
     <0x8 0x3>, <0xc 0x3>;
  };

  cpsw0_phy_gmii_sel: phy@4044 {
   compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
   ti,qsgmii-main-ports = <1>;
   reg = <0x4044 0x10>;
   #phy-cells = <1>;
  };

  usb_serdes_mux: mux-controller@4000 {
   compatible = "reg-mux";
   reg = <0x4000 0x4>;
   #mux-control-cells = <1>;
   mux-reg-masks = <0x0 0x8000000>;
  };
 };

 gic500: interrupt-controller@1800000 {
  compatible = "arm,gic-v3";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  #interrupt-cells = <3>;
  interrupt-controller;
  reg = <0x00 0x01800000 0x00 0x10000>,
        <0x00 0x01900000 0x00 0x100000>,
        <0x00 0x6f000000 0x00 0x2000>,
        <0x00 0x6f010000 0x00 0x1000>,
        <0x00 0x6f020000 0x00 0x2000>;


  interrupts = <1 9 4>;

  gic_its: msi-controller@1820000 {
   compatible = "arm,gic-v3-its";
   reg = <0x00 0x01820000 0x00 0x10000>;
   socionext,synquacer-pre-its = <0x1000000 0x400000>;
   msi-controller;
   #msi-cells = <1>;
  };
 };

 main_gpio_intr: interrupt-controller@a00000 {
  compatible = "ti,sci-intr";
  reg = <0x00 0x00a00000 0x00 0x800>;
  ti,intr-trigger-type = <1>;
  interrupt-controller;
  interrupt-parent = <&gic500>;
  #interrupt-cells = <1>;
  ti,sci = <&dmsc>;
  ti,sci-dev-id = <131>;
  ti,interrupt-ranges = <8 392 56>;
 };

 main_navss: bus@30000000 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
  ti,sci-dev-id = <199>;
  dma-coherent;
  dma-ranges;

  main_navss_intr: interrupt-controller@310e0000 {
   compatible = "ti,sci-intr";
   reg = <0x00 0x310e0000 0x00 0x4000>;
   ti,intr-trigger-type = <4>;
   interrupt-controller;
   interrupt-parent = <&gic500>;
   #interrupt-cells = <1>;
   ti,sci = <&dmsc>;
   ti,sci-dev-id = <213>;
   ti,interrupt-ranges = <0 64 64>,
           <64 448 64>,
           <128 672 64>;
  };

  main_udmass_inta: msi-controller@33d00000 {
   compatible = "ti,sci-inta";
   reg = <0x00 0x33d00000 0x00 0x100000>;
   interrupt-controller;
   #interrupt-cells = <0>;
   interrupt-parent = <&main_navss_intr>;
   msi-controller;
   ti,sci = <&dmsc>;
   ti,sci-dev-id = <209>;
   ti,interrupt-ranges = <0 0 256>;
  };

  secure_proxy_main: mailbox@32c00000 {
   compatible = "ti,am654-secure-proxy";
   #mbox-cells = <1>;
   reg-names = "target_data", "rt", "scfg";
   reg = <0x00 0x32c00000 0x00 0x100000>,
         <0x00 0x32400000 0x00 0x100000>,
         <0x00 0x32800000 0x00 0x100000>;
   interrupt-names = "rx_011";
   interrupts = <0 37 4>;
  };

  hwspinlock: spinlock@30e00000 {
   compatible = "ti,am654-hwspinlock";
   reg = <0x00 0x30e00000 0x00 0x1000>;
   #hwlock-cells = <1>;
  };

  mailbox0_cluster0: mailbox@31f80000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f80000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster1: mailbox@31f81000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f81000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster2: mailbox@31f82000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f82000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster3: mailbox@31f83000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f83000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster4: mailbox@31f84000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f84000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster5: mailbox@31f85000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f85000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster6: mailbox@31f86000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f86000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster7: mailbox@31f87000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f87000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster8: mailbox@31f88000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f88000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster9: mailbox@31f89000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f89000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster10: mailbox@31f8a000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f8a000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  mailbox0_cluster11: mailbox@31f8b000 {
   compatible = "ti,am654-mailbox";
   reg = <0x00 0x31f8b000 0x00 0x200>;
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <16>;
   interrupt-parent = <&main_navss_intr>;
   status = "disabled";
  };

  main_ringacc: ringacc@3c000000 {
   compatible = "ti,am654-navss-ringacc";
   reg = <0x00 0x3c000000 0x00 0x400000>,
         <0x00 0x38000000 0x00 0x400000>,
         <0x00 0x31120000 0x00 0x100>,
         <0x00 0x33000000 0x00 0x40000>,
         <0x00 0x31080000 0x00 0x40000>;
   reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
   ti,num-rings = <1024>;
   ti,sci-rm-range-gp-rings = <0x1>;
   ti,sci = <&dmsc>;
   ti,sci-dev-id = <211>;
   msi-parent = <&main_udmass_inta>;
  };

  main_udmap: dma-controller@31150000 {
   compatible = "ti,j721e-navss-main-udmap";
   reg = <0x00 0x31150000 0x00 0x100>,
         <0x00 0x34000000 0x00 0x100000>,
         <0x00 0x35000000 0x00 0x100000>,
         <0x00 0x30b00000 0x00 0x4000>,
         <0x00 0x30c00000 0x00 0x4000>,
         <0x00 0x30d00000 0x00 0x4000>;
   reg-names = "gcfg", "rchanrt", "tchanrt",
        "tchan", "rchan", "rflow";
   msi-parent = <&main_udmass_inta>;
   #dma-cells = <1>;

   ti,sci = <&dmsc>;
   ti,sci-dev-id = <212>;
   ti,ringacc = <&main_ringacc>;

   ti,sci-rm-range-tchan = <0x0d>,
      <0x0f>,
      <0x10>;
   ti,sci-rm-range-rchan = <0x0a>,
      <0x0b>,
      <0x0c>;
   ti,sci-rm-range-rflow = <0x00>;
  };

  cpts@310d0000 {
   compatible = "ti,j721e-cpts";
   reg = <0x00 0x310d0000 0x00 0x400>;
   reg-names = "cpts";
   clocks = <&k3_clks 201 1>;
   clock-names = "cpts";
   interrupts-extended = <&main_navss_intr 391>;
   interrupt-names = "cpts";
   ti,cpts-periodic-outputs = <6>;
   ti,cpts-ext-ts-inputs = <8>;
  };
 };

 cpsw0: ethernet@c000000 {
  compatible = "ti,j7200-cpswxg-nuss";
  #address-cells = <2>;
  #size-cells = <2>;
  reg = <0x00 0xc000000 0x00 0x200000>;
  reg-names = "cpsw_nuss";
  ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
  clocks = <&k3_clks 19 33>;
  clock-names = "fck";
  power-domains = <&k3_pds 19 1>;

  dmas = <&main_udmap 0xca00>,
         <&main_udmap 0xca01>,
         <&main_udmap 0xca02>,
         <&main_udmap 0xca03>,
         <&main_udmap 0xca04>,
         <&main_udmap 0xca05>,
         <&main_udmap 0xca06>,
         <&main_udmap 0xca07>,
         <&main_udmap 0x4a00>;
  dma-names = "tx0", "tx1", "tx2", "tx3",
       "tx4", "tx5", "tx6", "tx7",
       "rx";

  status = "disabled";

  ethernet-ports {
   #address-cells = <1>;
   #size-cells = <0>;
   cpsw0_port1: port@1 {
    reg = <1>;
    ti,mac-only;
    label = "port1";
    status = "disabled";
   };

   cpsw0_port2: port@2 {
    reg = <2>;
    ti,mac-only;
    label = "port2";
    status = "disabled";
   };

   cpsw0_port3: port@3 {
    reg = <3>;
    ti,mac-only;
    label = "port3";
    status = "disabled";
   };

   cpsw0_port4: port@4 {
    reg = <4>;
    ti,mac-only;
    label = "port4";
    status = "disabled";
   };
  };

  cpsw5g_mdio: mdio@f00 {
   compatible = "ti,cpsw-mdio","ti,davinci_mdio";
   reg = <0x00 0xf00 0x00 0x100>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&k3_clks 19 33>;
   clock-names = "fck";
   bus_freq = <1000000>;
   status = "disabled";
  };

  cpts@3d000 {
   compatible = "ti,j721e-cpts";
   reg = <0x00 0x3d000 0x00 0x400>;
   clocks = <&k3_clks 19 16>;
   clock-names = "cpts";
   interrupts-extended = <&gic500 0 16 4>;
   interrupt-names = "cpts";
   ti,cpts-ext-ts-inputs = <4>;
   ti,cpts-periodic-outputs = <2>;
  };
 };


 main_timerio_input: pinctrl@104200 {
  compatible = "ti,j7200-padconf", "pinctrl-single";
  reg = <0x0 0x104200 0x0 0x50>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0x000001ff>;
 };


 main_timerio_output: pinctrl@104280 {
  compatible = "ti,j7200-padconf", "pinctrl-single";
  reg = <0x0 0x104280 0x0 0x20>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0x0000001f>;
 };

 main_pmx0: pinctrl@11c000 {
  compatible = "ti,j7200-padconf", "pinctrl-single";

  reg = <0x00 0x11c000 0x00 0x10c>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0xffffffff>;
 };

 main_pmx1: pinctrl@11c11c {
  compatible = "ti,j7200-padconf", "pinctrl-single";

  reg = <0x00 0x11c11c 0x00 0xc>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0xffffffff>;
 };

 main_uart0: serial@2800000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02800000 0x00 0x100>;
  interrupts = <0 192 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 146 1>;
  clocks = <&k3_clks 146 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart1: serial@2810000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02810000 0x00 0x100>;
  interrupts = <0 193 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 278 1>;
  clocks = <&k3_clks 278 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart2: serial@2820000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02820000 0x00 0x100>;
  interrupts = <0 194 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 279 1>;
  clocks = <&k3_clks 279 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart3: serial@2830000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02830000 0x00 0x100>;
  interrupts = <0 195 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 280 1>;
  clocks = <&k3_clks 280 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart4: serial@2840000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02840000 0x00 0x100>;
  interrupts = <0 196 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 281 1>;
  clocks = <&k3_clks 281 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart5: serial@2850000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02850000 0x00 0x100>;
  interrupts = <0 197 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 282 1>;
  clocks = <&k3_clks 282 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart6: serial@2860000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02860000 0x00 0x100>;
  interrupts = <0 198 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 283 1>;
  clocks = <&k3_clks 283 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart7: serial@2870000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02870000 0x00 0x100>;
  interrupts = <0 199 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 284 1>;
  clocks = <&k3_clks 284 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart8: serial@2880000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02880000 0x00 0x100>;
  interrupts = <0 248 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 285 1>;
  clocks = <&k3_clks 285 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_uart9: serial@2890000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x02890000 0x00 0x100>;
  interrupts = <0 249 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 286 1>;
  clocks = <&k3_clks 286 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 main_i2c0: i2c@2000000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x2000000 0x00 0x100>;
  interrupts = <0 200 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 187 1>;
  power-domains = <&k3_pds 187 0>;
  status = "disabled";
 };

 main_i2c1: i2c@2010000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x2010000 0x00 0x100>;
  interrupts = <0 201 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 188 1>;
  power-domains = <&k3_pds 188 1>;
  status = "disabled";
 };

 main_i2c2: i2c@2020000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x2020000 0x00 0x100>;
  interrupts = <0 202 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 189 1>;
  power-domains = <&k3_pds 189 1>;
  status = "disabled";
 };

 main_i2c3: i2c@2030000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x2030000 0x00 0x100>;
  interrupts = <0 203 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 190 1>;
  power-domains = <&k3_pds 190 1>;
  status = "disabled";
 };

 main_i2c4: i2c@2040000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x2040000 0x00 0x100>;
  interrupts = <0 204 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 191 1>;
  power-domains = <&k3_pds 191 1>;
  status = "disabled";
 };

 main_i2c5: i2c@2050000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x2050000 0x00 0x100>;
  interrupts = <0 205 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 192 1>;
  power-domains = <&k3_pds 192 1>;
  status = "disabled";
 };

 main_i2c6: i2c@2060000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x2060000 0x00 0x100>;
  interrupts = <0 206 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 193 1>;
  power-domains = <&k3_pds 193 1>;
  status = "disabled";
 };

 main_sdhci0: mmc@4f80000 {
  compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
  reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
  interrupts = <0 3 4>;
  power-domains = <&k3_pds 91 1>;
  clock-names = "clk_ahb", "clk_xin";
  clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
  ti,otap-del-sel-legacy = <0x0>;
  ti,otap-del-sel-mmc-hs = <0x0>;
  ti,otap-del-sel-ddr52 = <0x6>;
  ti,otap-del-sel-hs200 = <0x8>;
  ti,otap-del-sel-hs400 = <0x5>;
  ti,itap-del-sel-legacy = <0x10>;
  ti,itap-del-sel-mmc-hs = <0xa>;
  ti,itap-del-sel-ddr52 = <0x3>;
  ti,strobe-sel = <0x77>;
  ti,clkbuf-sel = <0x7>;
  ti,trm-icp = <0x8>;
  bus-width = <8>;
  mmc-ddr-1_8v;
  mmc-hs200-1_8v;
  mmc-hs400-1_8v;
  dma-coherent;
  status = "disabled";
 };

 main_sdhci1: mmc@4fb0000 {
  compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
  reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
  interrupts = <0 4 4>;
  power-domains = <&k3_pds 92 1>;
  clock-names = "clk_ahb", "clk_xin";
  clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
  ti,otap-del-sel-legacy = <0x0>;
  ti,otap-del-sel-sd-hs = <0x0>;
  ti,otap-del-sel-sdr12 = <0xf>;
  ti,otap-del-sel-sdr25 = <0xf>;
  ti,otap-del-sel-sdr50 = <0xc>;
  ti,otap-del-sel-sdr104 = <0x5>;
  ti,otap-del-sel-ddr50 = <0xc>;
  ti,itap-del-sel-legacy = <0x0>;
  ti,itap-del-sel-sd-hs = <0x0>;
  ti,itap-del-sel-sdr12 = <0x0>;
  ti,itap-del-sel-sdr25 = <0x0>;
  ti,clkbuf-sel = <0x7>;
  ti,trm-icp = <0x8>;
  dma-coherent;
  status = "disabled";
 };

 serdes_wiz0: wiz@5060000 {
  compatible = "ti,j721e-wiz-10g";
  #address-cells = <1>;
  #size-cells = <1>;
  power-domains = <&k3_pds 292 1>;
  clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
  clock-names = "fck", "core_ref_clk", "ext_ref_clk";
  num-lanes = <4>;
  #reset-cells = <1>;
  ranges = <0x5060000 0x0 0x5060000 0x10000>;

  assigned-clocks = <&k3_clks 292 85>;
  assigned-clock-parents = <&k3_clks 292 89>;

  wiz0_pll0_refclk: pll0-refclk {
   clocks = <&k3_clks 292 85>, <&serdes_refclk>;
   clock-output-names = "wiz0_pll0_refclk";
   #clock-cells = <0>;
   assigned-clocks = <&wiz0_pll0_refclk>;
   assigned-clock-parents = <&k3_clks 292 85>;
  };

  wiz0_pll1_refclk: pll1-refclk {
   clocks = <&k3_clks 292 85>, <&serdes_refclk>;
   clock-output-names = "wiz0_pll1_refclk";
   #clock-cells = <0>;
   assigned-clocks = <&wiz0_pll1_refclk>;
   assigned-clock-parents = <&k3_clks 292 85>;
  };

  wiz0_refclk_dig: refclk-dig {
   clocks = <&k3_clks 292 85>, <&serdes_refclk>;
   clock-output-names = "wiz0_refclk_dig";
   #clock-cells = <0>;
   assigned-clocks = <&wiz0_refclk_dig>;
   assigned-clock-parents = <&k3_clks 292 85>;
  };

  wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
   clocks = <&wiz0_refclk_dig>;
   #clock-cells = <0>;
  };

  serdes0: serdes@5060000 {
   compatible = "ti,j721e-serdes-10g";
   reg = <0x05060000 0x00010000>;
   reg-names = "torrent_phy";
   resets = <&serdes_wiz0 0>;
   reset-names = "torrent_reset";
   clocks = <&wiz0_pll0_refclk>;
   clock-names = "refclk";
   #address-cells = <1>;
   #size-cells = <0>;
  };
 };

 pcie1_rc: pcie@2910000 {
  compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
  reg = <0x00 0x02910000 0x00 0x1000>,
        <0x00 0x02917000 0x00 0x400>,
        <0x00 0x0d800000 0x00 0x00800000>,
        <0x00 0x18000000 0x00 0x00001000>;
  reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
  interrupt-names = "link_state";
  interrupts = <0 330 1>;
  device_type = "pci";
  ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
  max-link-speed = <3>;
  num-lanes = <4>;
  power-domains = <&k3_pds 240 1>;
  clocks = <&k3_clks 240 6>;
  clock-names = "fck";
  #address-cells = <3>;
  #size-cells = <2>;
  bus-range = <0x0 0xff>;
  cdns,no-bar-match-nbits = <64>;
  vendor-id = <0x104c>;
  device-id = <0xb00f>;
  msi-map = <0x0 &gic_its 0x0 0x10000>;
  dma-coherent;
  ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
    <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
  dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
  status = "disabled";
 };

 usbss0: cdns-usb@4104000 {
  compatible = "ti,j721e-usb";
  reg = <0x00 0x4104000 0x00 0x100>;
  dma-coherent;
  power-domains = <&k3_pds 288 1>;
  clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
  clock-names = "ref", "lpm";
  assigned-clocks = <&k3_clks 288 12>;
  assigned-clock-parents = <&k3_clks 288 13>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  usb0: usb@6000000 {
   compatible = "cdns,usb3";
   reg = <0x00 0x6000000 0x00 0x10000>,
         <0x00 0x6010000 0x00 0x10000>,
         <0x00 0x6020000 0x00 0x10000>;
   reg-names = "otg", "xhci", "dev";
   interrupts = <0 96 4>,
         <0 102 4>,
         <0 120 4>;
   interrupt-names = "host",
       "peripheral",
       "otg";
   maximum-speed = "super-speed";
   dr_mode = "otg";
   cdns,phyrst-a-enable;
  };
 };

 main_gpio0: gpio@600000 {
  compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  reg = <0x00 0x00600000 0x00 0x100>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-parent = <&main_gpio_intr>;
  interrupts = <145>, <146>, <147>, <148>,
        <149>;
  interrupt-controller;
  #interrupt-cells = <2>;
  ti,ngpio = <69>;
  ti,davinci-gpio-unbanked = <0>;
  power-domains = <&k3_pds 105 1>;
  clocks = <&k3_clks 105 0>;
  clock-names = "gpio";
  status = "disabled";
 };

 main_gpio2: gpio@610000 {
  compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  reg = <0x00 0x00610000 0x00 0x100>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-parent = <&main_gpio_intr>;
  interrupts = <154>, <155>, <156>, <157>,
        <158>;
  interrupt-controller;
  #interrupt-cells = <2>;
  ti,ngpio = <69>;
  ti,davinci-gpio-unbanked = <0>;
  power-domains = <&k3_pds 107 1>;
  clocks = <&k3_clks 107 0>;
  clock-names = "gpio";
  status = "disabled";
 };

 main_gpio4: gpio@620000 {
  compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  reg = <0x00 0x00620000 0x00 0x100>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-parent = <&main_gpio_intr>;
  interrupts = <163>, <164>, <165>, <166>,
        <167>;
  interrupt-controller;
  #interrupt-cells = <2>;
  ti,ngpio = <69>;
  ti,davinci-gpio-unbanked = <0>;
  power-domains = <&k3_pds 109 1>;
  clocks = <&k3_clks 109 0>;
  clock-names = "gpio";
  status = "disabled";
 };

 main_gpio6: gpio@630000 {
  compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  reg = <0x00 0x00630000 0x00 0x100>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-parent = <&main_gpio_intr>;
  interrupts = <172>, <173>, <174>, <175>,
        <176>;
  interrupt-controller;
  #interrupt-cells = <2>;
  ti,ngpio = <69>;
  ti,davinci-gpio-unbanked = <0>;
  power-domains = <&k3_pds 111 1>;
  clocks = <&k3_clks 111 0>;
  clock-names = "gpio";
  status = "disabled";
 };

 main_mcan0: can@2701000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02701000 0x00 0x200>,
        <0x00 0x02708000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 156 1>;
  clocks = <&k3_clks 156 0>, <&k3_clks 156 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 124 4>,
        <0 125 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan1: can@2711000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02711000 0x00 0x200>,
        <0x00 0x02718000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 158 1>;
  clocks = <&k3_clks 158 0>, <&k3_clks 158 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 127 4>,
        <0 128 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan2: can@2721000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02721000 0x00 0x200>,
        <0x00 0x02728000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 160 1>;
  clocks = <&k3_clks 160 0>, <&k3_clks 160 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 130 4>,
        <0 131 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan3: can@2731000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02731000 0x00 0x200>,
        <0x00 0x02738000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 161 1>;
  clocks = <&k3_clks 161 0>, <&k3_clks 161 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 133 4>,
        <0 134 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan4: can@2741000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02741000 0x00 0x200>,
        <0x00 0x02748000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 162 1>;
  clocks = <&k3_clks 162 0>, <&k3_clks 162 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 136 4>,
        <0 137 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan5: can@2751000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02751000 0x00 0x200>,
        <0x00 0x02758000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 163 1>;
  clocks = <&k3_clks 163 0>, <&k3_clks 163 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 139 4>,
        <0 140 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan6: can@2761000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02761000 0x00 0x200>,
        <0x00 0x02768000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 164 1>;
  clocks = <&k3_clks 164 0>, <&k3_clks 164 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 142 4>,
        <0 143 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan7: can@2771000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02771000 0x00 0x200>,
        <0x00 0x02778000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 165 1>;
  clocks = <&k3_clks 165 0>, <&k3_clks 165 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 145 4>,
        <0 146 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan8: can@2781000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02781000 0x00 0x200>,
        <0x00 0x02788000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 166 1>;
  clocks = <&k3_clks 166 0>, <&k3_clks 166 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 576 4>,
        <0 577 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan9: can@2791000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02791000 0x00 0x200>,
        <0x00 0x02798000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 167 1>;
  clocks = <&k3_clks 167 0>, <&k3_clks 167 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 579 4>,
        <0 580 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan10: can@27a1000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x027a1000 0x00 0x200>,
        <0x00 0x027a8000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 168 1>;
  clocks = <&k3_clks 168 0>, <&k3_clks 168 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 582 4>,
        <0 583 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan11: can@27b1000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x027b1000 0x00 0x200>,
        <0x00 0x027b8000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 169 1>;
  clocks = <&k3_clks 169 0>, <&k3_clks 169 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 585 4>,
        <0 586 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan12: can@27c1000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x027c1000 0x00 0x200>,
        <0x00 0x027c8000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 170 1>;
  clocks = <&k3_clks 170 0>, <&k3_clks 170 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 588 4>,
        <0 589 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan13: can@27d1000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x027d1000 0x00 0x200>,
        <0x00 0x027d8000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 171 1>;
  clocks = <&k3_clks 171 0>, <&k3_clks 171 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 591 4>,
        <0 592 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan14: can@2681000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02681000 0x00 0x200>,
        <0x00 0x02688000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 150 1>;
  clocks = <&k3_clks 150 0>, <&k3_clks 150 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 594 4>,
        <0 595 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan15: can@2691000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x02691000 0x00 0x200>,
        <0x00 0x02698000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 151 1>;
  clocks = <&k3_clks 151 0>, <&k3_clks 151 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 597 4>,
        <0 598 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan16: can@26a1000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x026a1000 0x00 0x200>,
        <0x00 0x026a8000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 152 1>;
  clocks = <&k3_clks 152 0>, <&k3_clks 152 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 784 4>,
        <0 785 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_mcan17: can@26b1000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x026b1000 0x00 0x200>,
        <0x00 0x026b8000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 153 1>;
  clocks = <&k3_clks 153 0>, <&k3_clks 153 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 787 4>,
        <0 788 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 main_spi0: spi@2100000 {
  compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  reg = <0x00 0x02100000 0x00 0x400>;
  interrupts = <0 184 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 266 1>;
  clocks = <&k3_clks 266 1>;
  status = "disabled";
 };

 main_spi1: spi@2110000 {
  compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  reg = <0x00 0x02110000 0x00 0x400>;
  interrupts = <0 185 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 267 1>;
  clocks = <&k3_clks 267 1>;
  status = "disabled";
 };

 main_spi2: spi@2120000 {
  compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  reg = <0x00 0x02120000 0x00 0x400>;
  interrupts = <0 186 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 268 1>;
  clocks = <&k3_clks 268 1>;
  status = "disabled";
 };

 main_spi3: spi@2130000 {
  compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  reg = <0x00 0x02130000 0x00 0x400>;
  interrupts = <0 187 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 269 1>;
  clocks = <&k3_clks 269 1>;
  status = "disabled";
 };

 main_spi4: spi@2140000 {
  compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  reg = <0x00 0x02140000 0x00 0x400>;
  interrupts = <0 188 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 270 1>;
  clocks = <&k3_clks 270 1>;
  status = "disabled";
 };

 main_spi5: spi@2150000 {
  compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  reg = <0x00 0x02150000 0x00 0x400>;
  interrupts = <0 189 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 271 1>;
  clocks = <&k3_clks 271 1>;
  status = "disabled";
 };

 main_spi6: spi@2160000 {
  compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  reg = <0x00 0x02160000 0x00 0x400>;
  interrupts = <0 190 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 272 1>;
  clocks = <&k3_clks 272 1>;
  status = "disabled";
 };

 main_spi7: spi@2170000 {
  compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  reg = <0x00 0x02170000 0x00 0x400>;
  interrupts = <0 191 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 273 1>;
  clocks = <&k3_clks 273 1>;
  status = "disabled";
 };

 watchdog0: watchdog@2200000 {
  compatible = "ti,j7-rti-wdt";
  reg = <0x0 0x2200000 0x0 0x100>;
  clocks = <&k3_clks 252 1>;
  power-domains = <&k3_pds 252 1>;
  assigned-clocks = <&k3_clks 252 1>;
  assigned-clock-parents = <&k3_clks 252 5>;
 };

 watchdog1: watchdog@2210000 {
  compatible = "ti,j7-rti-wdt";
  reg = <0x0 0x2210000 0x0 0x100>;
  clocks = <&k3_clks 253 1>;
  power-domains = <&k3_pds 253 1>;
  assigned-clocks = <&k3_clks 253 1>;
  assigned-clock-parents = <&k3_clks 253 5>;
 };

 main_timer0: timer@2400000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2400000 0x00 0x400>;
  interrupts = <0 224 4>;
  clocks = <&k3_clks 49 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 49 1>;
  assigned-clock-parents = <&k3_clks 49 2>;
  power-domains = <&k3_pds 49 1>;
  ti,timer-pwm;
  status = "reserved";
 };

 main_timer1: timer@2410000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2410000 0x00 0x400>;
  interrupts = <0 225 4>;
  clocks = <&k3_clks 50 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
  assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
  power-domains = <&k3_pds 50 1>;
  ti,timer-pwm;
  status = "reserved";
 };

 main_timer2: timer@2420000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2420000 0x00 0x400>;
  interrupts = <0 226 4>;
  clocks = <&k3_clks 51 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 51 1>;
  assigned-clock-parents = <&k3_clks 51 2>;
  power-domains = <&k3_pds 51 1>;
  ti,timer-pwm;
  status = "reserved";
 };

 main_timer3: timer@2430000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2430000 0x00 0x400>;
  interrupts = <0 227 4>;
  clocks = <&k3_clks 52 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
  assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
  power-domains = <&k3_pds 52 1>;
  ti,timer-pwm;
 };

 main_timer4: timer@2440000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2440000 0x00 0x400>;
  interrupts = <0 228 4>;
  clocks = <&k3_clks 53 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 53 1>;
  assigned-clock-parents = <&k3_clks 53 2>;
  power-domains = <&k3_pds 53 1>;
  ti,timer-pwm;
 };

 main_timer5: timer@2450000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2450000 0x00 0x400>;
  interrupts = <0 229 4>;
  clocks = <&k3_clks 54 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
  assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
  power-domains = <&k3_pds 54 1>;
  ti,timer-pwm;
 };

 main_timer6: timer@2460000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2460000 0x00 0x400>;
  interrupts = <0 230 4>;
  clocks = <&k3_clks 55 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 55 1>;
  assigned-clock-parents = <&k3_clks 55 2>;
  power-domains = <&k3_pds 55 1>;
  ti,timer-pwm;
 };

 main_timer7: timer@2470000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2470000 0x00 0x400>;
  interrupts = <0 231 4>;
  clocks = <&k3_clks 57 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
  assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
  power-domains = <&k3_pds 57 1>;
  ti,timer-pwm;
 };

 main_timer8: timer@2480000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2480000 0x00 0x400>;
  interrupts = <0 232 4>;
  clocks = <&k3_clks 58 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 58 1>;
  assigned-clock-parents = <&k3_clks 58 2>;
  power-domains = <&k3_pds 58 1>;
  ti,timer-pwm;
 };

 main_timer9: timer@2490000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2490000 0x00 0x400>;
  interrupts = <0 233 4>;
  clocks = <&k3_clks 59 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
  assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
  power-domains = <&k3_pds 59 1>;
  ti,timer-pwm;
 };

 main_timer10: timer@24a0000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x24a0000 0x00 0x400>;
  interrupts = <0 234 4>;
  clocks = <&k3_clks 60 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 60 1>;
  assigned-clock-parents = <&k3_clks 60 2>;
  power-domains = <&k3_pds 60 1>;
  ti,timer-pwm;
 };

 main_timer11: timer@24b0000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x24b0000 0x00 0x400>;
  interrupts = <0 235 4>;
  clocks = <&k3_clks 62 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
  assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
  power-domains = <&k3_pds 62 1>;
  ti,timer-pwm;
 };

 main_timer12: timer@24c0000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x24c0000 0x00 0x400>;
  interrupts = <0 236 4>;
  clocks = <&k3_clks 63 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 63 1>;
  assigned-clock-parents = <&k3_clks 63 2>;
  power-domains = <&k3_pds 63 1>;
  ti,timer-pwm;
 };

 main_timer13: timer@24d0000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x24d0000 0x00 0x400>;
  interrupts = <0 237 4>;
  clocks = <&k3_clks 64 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
  assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
  power-domains = <&k3_pds 64 1>;
  ti,timer-pwm;
 };

 main_timer14: timer@24e0000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x24e0000 0x00 0x400>;
  interrupts = <0 238 4>;
  clocks = <&k3_clks 65 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 65 1>;
  assigned-clock-parents = <&k3_clks 65 2>;
  power-domains = <&k3_pds 65 1>;
  ti,timer-pwm;
 };

 main_timer15: timer@24f0000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x24f0000 0x00 0x400>;
  interrupts = <0 239 4>;
  clocks = <&k3_clks 66 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
  assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
  power-domains = <&k3_pds 66 1>;
  ti,timer-pwm;
 };

 main_timer16: timer@2500000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2500000 0x00 0x400>;
  interrupts = <0 240 4>;
  clocks = <&k3_clks 67 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 67 1>;
  assigned-clock-parents = <&k3_clks 67 2>;
  power-domains = <&k3_pds 67 1>;
  ti,timer-pwm;
 };

 main_timer17: timer@2510000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2510000 0x00 0x400>;
  interrupts = <0 241 4>;
  clocks = <&k3_clks 68 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
  assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
  power-domains = <&k3_pds 68 1>;
  ti,timer-pwm;
 };

 main_timer18: timer@2520000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2520000 0x00 0x400>;
  interrupts = <0 242 4>;
  clocks = <&k3_clks 69 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 69 1>;
  assigned-clock-parents = <&k3_clks 69 2>;
  power-domains = <&k3_pds 69 1>;
  ti,timer-pwm;
 };

 main_timer19: timer@2530000 {
  compatible = "ti,am654-timer";
  reg = <0x00 0x2530000 0x00 0x400>;
  interrupts = <0 243 4>;
  clocks = <&k3_clks 70 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
  assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
  power-domains = <&k3_pds 70 1>;
  ti,timer-pwm;
 };

 main_r5fss0: r5fss@5c00000 {
  compatible = "ti,j7200-r5fss";
  ti,cluster-mode = <0>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
    <0x5d00000 0x00 0x5d00000 0x20000>;
  power-domains = <&k3_pds 243 1>;

  main_r5fss0_core0: r5f@5c00000 {
   compatible = "ti,j7200-r5f";
   reg = <0x5c00000 0x00010000>,
         <0x5c10000 0x00010000>;
   reg-names = "atcm", "btcm";
   ti,sci = <&dmsc>;
   ti,sci-dev-id = <245>;
   ti,sci-proc-ids = <0x06 0xff>;
   resets = <&k3_reset 245 1>;
   firmware-name = "j7200-main-r5f0_0-fw";
   ti,atcm-enable = <1>;
   ti,btcm-enable = <1>;
   ti,loczrama = <1>;
  };

  main_r5fss0_core1: r5f@5d00000 {
   compatible = "ti,j7200-r5f";
   reg = <0x5d00000 0x00008000>,
         <0x5d10000 0x00008000>;
   reg-names = "atcm", "btcm";
   ti,sci = <&dmsc>;
   ti,sci-dev-id = <246>;
   ti,sci-proc-ids = <0x07 0xff>;
   resets = <&k3_reset 246 1>;
   firmware-name = "j7200-main-r5f0_1-fw";
   ti,atcm-enable = <1>;
   ti,btcm-enable = <1>;
   ti,loczrama = <1>;
  };
 };

 main_esm: esm@700000 {
  compatible = "ti,j721e-esm";
  reg = <0x0 0x700000 0x0 0x1000>;
  ti,esm-pins = <656>, <657>;
 };

 timesync_router: pinctrl@a40000 {
  compatible = "pinctrl-single";
  reg = <0x0 0xa40000 0x0 0x800>;
  #address-cells = <1>;
  #size-cells = <0>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0x000107ff>;
  status = "disabled";
 };
};
# 311 "arch/arm64/boot/dts/company_name/custom-board.dts" 2
# 1 "arch/arm64/boot/dts/company_name/../ti/k3-j7200-mcu-wakeup.dtsi" 1







&cbass_mcu_wakeup {
 dmsc: system-controller@44083000 {
  compatible = "ti,k2g-sci";
  ti,host-id = <12>;

  mbox-names = "rx", "tx";

  mboxes = <&secure_proxy_main 11>,
    <&secure_proxy_main 13>;

  reg-names = "debug_messages";
  reg = <0x00 0x44083000 0x00 0x1000>;

  k3_pds: power-controller {
   compatible = "ti,sci-pm-domain";
   #power-domain-cells = <2>;
  };

  k3_clks: clock-controller {
   compatible = "ti,k2g-sci-clk";
   #clock-cells = <2>;
  };

  k3_reset: reset-controller {
   compatible = "ti,sci-reset";
   #reset-cells = <2>;
  };
 };

 mcu_timer0: timer@40400000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40400000 0x00 0x400>;
  interrupts = <0 816 4>;
  clocks = <&k3_clks 35 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 35 1>;
  assigned-clock-parents = <&k3_clks 35 2>;
  power-domains = <&k3_pds 35 1>;
  ti,timer-pwm;
 };

 mcu_timer1: timer@40410000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40410000 0x00 0x400>;
  interrupts = <0 817 4>;
  clocks = <&k3_clks 71 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
  assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
  power-domains = <&k3_pds 71 1>;
  ti,timer-pwm;
 };

 mcu_timer2: timer@40420000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40420000 0x00 0x400>;
  interrupts = <0 818 4>;
  clocks = <&k3_clks 72 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 72 1>;
  assigned-clock-parents = <&k3_clks 72 2>;
  power-domains = <&k3_pds 72 1>;
  ti,timer-pwm;
 };

 mcu_timer3: timer@40430000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40430000 0x00 0x400>;
  interrupts = <0 819 4>;
  clocks = <&k3_clks 73 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
  assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
  power-domains = <&k3_pds 73 1>;
  ti,timer-pwm;
 };

 mcu_timer4: timer@40440000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40440000 0x00 0x400>;
  interrupts = <0 820 4>;
  clocks = <&k3_clks 74 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 74 1>;
  assigned-clock-parents = <&k3_clks 74 2>;
  power-domains = <&k3_pds 74 1>;
  ti,timer-pwm;
 };

 mcu_timer5: timer@40450000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40450000 0x00 0x400>;
  interrupts = <0 821 4>;
  clocks = <&k3_clks 75 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
  assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
  power-domains = <&k3_pds 75 1>;
  ti,timer-pwm;
 };

 mcu_timer6: timer@40460000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40460000 0x00 0x400>;
  interrupts = <0 822 4>;
  clocks = <&k3_clks 76 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 76 1>;
  assigned-clock-parents = <&k3_clks 76 2>;
  power-domains = <&k3_pds 76 1>;
  ti,timer-pwm;
 };

 mcu_timer7: timer@40470000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40470000 0x00 0x400>;
  interrupts = <0 823 4>;
  clocks = <&k3_clks 77 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
  assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
  power-domains = <&k3_pds 77 1>;
  ti,timer-pwm;
 };

 mcu_timer8: timer@40480000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40480000 0x00 0x400>;
  interrupts = <0 824 4>;
  clocks = <&k3_clks 78 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 78 1>;
  assigned-clock-parents = <&k3_clks 78 2>;
  power-domains = <&k3_pds 78 1>;
  ti,timer-pwm;
 };

 mcu_timer9: timer@40490000 {
  status = "reserved";
  compatible = "ti,am654-timer";
  reg = <0x00 0x40490000 0x00 0x400>;
  interrupts = <0 825 4>;
  clocks = <&k3_clks 79 1>;
  clock-names = "fck";
  assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
  assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
  power-domains = <&k3_pds 79 1>;
  ti,timer-pwm;
 };

 mcu_conf: syscon@40f00000 {
  compatible = "syscon", "simple-mfd";
  reg = <0x00 0x40f00000 0x00 0x20000>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x00 0x00 0x40f00000 0x20000>;

  phy_gmii_sel: phy@4040 {
   compatible = "ti,am654-phy-gmii-sel";
   reg = <0x4040 0x4>;
   #phy-cells = <1>;
  };
 };

 wkup_conf: bus@43000000 {
  compatible = "simple-bus";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x0 0x00 0x43000000 0x20000>;

  chipid: chipid@14 {
   compatible = "ti,am654-chipid";
   reg = <0x14 0x4>;
  };
 };


 mcu_timerio_input: pinctrl@40f04200 {
  compatible = "ti,j7200-padconf", "pinctrl-single";
  reg = <0x0 0x40f04200 0x0 0x28>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0x0000000F>;
  status = "reserved";
 };


 mcu_timerio_output: pinctrl@40f04280 {
  compatible = "ti,j7200-padconf", "pinctrl-single";
  reg = <0x0 0x40f04280 0x0 0x28>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0x0000000F>;
  status = "reserved";
 };

 wkup_pmx0: pinctrl@4301c000 {
  compatible = "ti,j7200-padconf", "pinctrl-single";

  reg = <0x00 0x4301c000 0x00 0x34>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0xffffffff>;
 };

 wkup_pmx1: pinctrl@4301c038 {
  compatible = "ti,j7200-padconf", "pinctrl-single";

  reg = <0x00 0x4301c038 0x00 0x8>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0xffffffff>;
 };

 wkup_pmx2: pinctrl@4301c068 {
  compatible = "ti,j7200-padconf", "pinctrl-single";

  reg = <0x00 0x4301c068 0x00 0xec>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0xffffffff>;
 };

 wkup_pmx3: pinctrl@4301c174 {
  compatible = "ti,j7200-padconf", "pinctrl-single";

  reg = <0x00 0x4301c174 0x00 0x20>;
  #pinctrl-cells = <1>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0xffffffff>;
 };

 mcu_ram: sram@41c00000 {
  compatible = "mmio-sram";
  reg = <0x00 0x41c00000 0x00 0x100000>;
  ranges = <0x00 0x00 0x41c00000 0x100000>;
  #address-cells = <1>;
  #size-cells = <1>;
 };

 wkup_uart0: serial@42300000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x42300000 0x00 0x100>;
  interrupts = <0 897 4>;
  clock-frequency = <48000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 287 1>;
  clocks = <&k3_clks 287 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 mcu_uart0: serial@40a00000 {
  compatible = "ti,j721e-uart", "ti,am654-uart";
  reg = <0x00 0x40a00000 0x00 0x100>;
  interrupts = <0 846 4>;
  clock-frequency = <96000000>;
  current-speed = <115200>;
  power-domains = <&k3_pds 149 1>;
  clocks = <&k3_clks 149 2>;
  clock-names = "fclk";
  status = "disabled";
 };

 wkup_gpio_intr: interrupt-controller@42200000 {
  compatible = "ti,sci-intr";
  reg = <0x00 0x42200000 0x00 0x400>;
  ti,intr-trigger-type = <1>;
  interrupt-controller;
  interrupt-parent = <&gic500>;
  #interrupt-cells = <1>;
  ti,sci = <&dmsc>;
  ti,sci-dev-id = <137>;
  ti,interrupt-ranges = <16 960 16>;
 };

 wkup_gpio0: gpio@42110000 {
  compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  reg = <0x00 0x42110000 0x00 0x100>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-parent = <&wkup_gpio_intr>;
  interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
  interrupt-controller;
  #interrupt-cells = <2>;
  ti,ngpio = <85>;
  ti,davinci-gpio-unbanked = <0>;
  power-domains = <&k3_pds 113 1>;
  clocks = <&k3_clks 113 0>;
  clock-names = "gpio";
  status = "disabled";
 };

 wkup_gpio1: gpio@42100000 {
  compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  reg = <0x00 0x42100000 0x00 0x100>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-parent = <&wkup_gpio_intr>;
  interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
  interrupt-controller;
  #interrupt-cells = <2>;
  ti,ngpio = <85>;
  ti,davinci-gpio-unbanked = <0>;
  power-domains = <&k3_pds 114 1>;
  clocks = <&k3_clks 114 0>;
  clock-names = "gpio";
  status = "disabled";
 };

 mcu_navss: bus@28380000 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
  dma-coherent;
  dma-ranges;
  ti,sci-dev-id = <232>;

  mcu_ringacc: ringacc@2b800000 {
   compatible = "ti,am654-navss-ringacc";
   reg = <0x00 0x2b800000 0x00 0x400000>,
         <0x00 0x2b000000 0x00 0x400000>,
         <0x00 0x28590000 0x00 0x100>,
         <0x00 0x2a500000 0x00 0x40000>,
         <0x00 0x28440000 0x00 0x40000>;
   reg-names = "rt", "fifos", "proxy_gcfg",
        "proxy_target", "cfg";
   ti,num-rings = <286>;
   ti,sci-rm-range-gp-rings = <0x1>;
   ti,sci = <&dmsc>;
   ti,sci-dev-id = <235>;
   msi-parent = <&main_udmass_inta>;
  };

  mcu_udmap: dma-controller@285c0000 {
   compatible = "ti,j721e-navss-mcu-udmap";
   reg = <0x00 0x285c0000 0x00 0x100>,
         <0x00 0x2a800000 0x00 0x40000>,
         <0x00 0x2aa00000 0x00 0x40000>,
         <0x00 0x284a0000 0x00 0x4000>,
         <0x00 0x284c0000 0x00 0x4000>,
         <0x00 0x28400000 0x00 0x2000>;
   reg-names = "gcfg", "rchanrt", "tchanrt",
        "tchan", "rchan", "rflow";
   msi-parent = <&main_udmass_inta>;
   #dma-cells = <1>;

   ti,sci = <&dmsc>;
   ti,sci-dev-id = <236>;
   ti,ringacc = <&mcu_ringacc>;

   ti,sci-rm-range-tchan = <0x0d>,
      <0x0f>;
   ti,sci-rm-range-rchan = <0x0a>,
      <0x0b>;
   ti,sci-rm-range-rflow = <0x00>;
  };
 };

 secure_proxy_mcu: mailbox@2a480000 {
  compatible = "ti,am654-secure-proxy";
  #mbox-cells = <1>;
  reg-names = "target_data", "rt", "scfg";
  reg = <0x0 0x2a480000 0x0 0x80000>,
        <0x0 0x2a380000 0x0 0x80000>,
        <0x0 0x2a400000 0x0 0x80000>;





  status = "disabled";
 };

 mcu_cpsw: ethernet@46000000 {
  compatible = "ti,j721e-cpsw-nuss";
  #address-cells = <2>;
  #size-cells = <2>;
  reg = <0x00 0x46000000 0x00 0x200000>;
  reg-names = "cpsw_nuss";
  ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
  dma-coherent;
  clocks = <&k3_clks 18 21>;
  clock-names = "fck";
  power-domains = <&k3_pds 18 1>;

  dmas = <&mcu_udmap 0xf000>,
         <&mcu_udmap 0xf001>,
         <&mcu_udmap 0xf002>,
         <&mcu_udmap 0xf003>,
         <&mcu_udmap 0xf004>,
         <&mcu_udmap 0xf005>,
         <&mcu_udmap 0xf006>,
         <&mcu_udmap 0xf007>,
         <&mcu_udmap 0x7000>;
  dma-names = "tx0", "tx1", "tx2", "tx3",
       "tx4", "tx5", "tx6", "tx7",
       "rx";

  ethernet-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   cpsw_port1: port@1 {
    reg = <1>;
    ti,mac-only;
    label = "port1";
    ti,syscon-efuse = <&mcu_conf 0x200>;
    phys = <&phy_gmii_sel 1>;
   };
  };

  davinci_mdio: mdio@f00 {
   compatible = "ti,cpsw-mdio","ti,davinci_mdio";
   reg = <0x00 0xf00 0x00 0x100>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&k3_clks 18 21>;
   clock-names = "fck";
   bus_freq = <1000000>;
  };

  cpts@3d000 {
   compatible = "ti,am65-cpts";
   reg = <0x00 0x3d000 0x00 0x400>;
   clocks = <&k3_clks 18 2>;
   clock-names = "cpts";
   interrupts-extended = <&gic500 0 858 4>;
   interrupt-names = "cpts";
   ti,cpts-ext-ts-inputs = <4>;
   ti,cpts-periodic-outputs = <2>;
  };
 };

 mcu_i2c0: i2c@40b00000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x40b00000 0x00 0x100>;
  interrupts = <0 852 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 194 1>;
  power-domains = <&k3_pds 194 1>;
  status = "disabled";
 };

 mcu_i2c1: i2c@40b10000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x40b10000 0x00 0x100>;
  interrupts = <0 853 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 195 1>;
  power-domains = <&k3_pds 195 1>;
  status = "disabled";
 };

 wkup_i2c0: i2c@42120000 {
  compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  reg = <0x00 0x42120000 0x00 0x100>;
  interrupts = <0 896 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "fck";
  clocks = <&k3_clks 197 1>;
  power-domains = <&k3_pds 197 0>;
  status = "disabled";
 };

 mcu_spi0: spi@40300000 {
  compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
  reg = <0x00 0x040300000 0x00 0x400>;
  interrupts = <0 848 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 274 1>;
  clocks = <&k3_clks 274 0>;
  status = "disabled";
 };

 mcu_spi1: spi@40310000 {
  compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
  reg = <0x00 0x040310000 0x00 0x400>;
  interrupts = <0 849 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 275 1>;
  clocks = <&k3_clks 275 0>;
  status = "disabled";
 };

 mcu_spi2: spi@40320000 {
  compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
  reg = <0x00 0x040320000 0x00 0x400>;
  interrupts = <0 850 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  power-domains = <&k3_pds 276 1>;
  clocks = <&k3_clks 276 0>;
  status = "disabled";
 };

 fss: bus@47000000 {
  compatible = "simple-bus";
  reg = <0x00 0x47000000 0x00 0x100>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  hbmc_mux: mux-controller@47000004 {
   compatible = "reg-mux";
   reg = <0x00 0x47000004 0x00 0x4>;
   #mux-control-cells = <1>;
   mux-reg-masks = <0x0 0x2>;
  };

  hbmc: hyperbus@47034000 {
   compatible = "ti,am654-hbmc";
   reg = <0x00 0x47034000 0x00 0x100>,
    <0x05 0x00000000 0x01 0x0000000>;
   power-domains = <&k3_pds 102 1>;
   clocks = <&k3_clks 102 0>;
   assigned-clocks = <&k3_clks 102 5>;
   assigned-clock-rates = <333333333>;
   #address-cells = <2>;
   #size-cells = <1>;
   mux-controls = <&hbmc_mux 0>;
  };

  ospi0: spi@47040000 {
   compatible = "ti,am654-ospi", "cdns,qspi-nor";
   reg = <0x0 0x47040000 0x0 0x100>,
         <0x5 0x00000000 0x1 0x0000000>;
   interrupts = <0 840 4>;
   cdns,fifo-depth = <256>;
   cdns,fifo-width = <4>;
   cdns,trigger-address = <0x0>;
   clocks = <&k3_clks 103 0>;
   assigned-clocks = <&k3_clks 103 0>;
   assigned-clock-parents = <&k3_clks 103 2>;
   assigned-clock-rates = <166666666>;
   power-domains = <&k3_pds 103 1>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };
 };

 tscadc0: tscadc@40200000 {
  compatible = "ti,am3359-tscadc";
  reg = <0x00 0x40200000 0x00 0x1000>;
  interrupts = <0 860 4>;
  power-domains = <&k3_pds 0 1>;
  clocks = <&k3_clks 0 1>;
  assigned-clocks = <&k3_clks 0 3>;
  assigned-clock-rates = <60000000>;
  clock-names = "fck";
  dmas = <&main_udmap 0x7400>,
   <&main_udmap 0x7401>;
  dma-names = "fifo0", "fifo1";

  adc {
   #io-channel-cells = <1>;
   compatible = "ti,am3359-adc";
  };
 };

 mcu_r5fss0: r5fss@41000000 {
  compatible = "ti,j7200-r5fss";
  ti,cluster-mode = <1>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x41000000 0x00 0x41000000 0x20000>,
    <0x41400000 0x00 0x41400000 0x20000>;
  power-domains = <&k3_pds 249 1>;

  mcu_r5fss0_core0: r5f@41000000 {
   compatible = "ti,j7200-r5f";
   reg = <0x41000000 0x00010000>,
         <0x41010000 0x00010000>;
   reg-names = "atcm", "btcm";
   ti,sci = <&dmsc>;
   ti,sci-dev-id = <250>;
   ti,sci-proc-ids = <0x01 0xff>;
   resets = <&k3_reset 250 1>;
   firmware-name = "j7200-mcu-r5f0_0-fw";
   ti,atcm-enable = <1>;
   ti,btcm-enable = <1>;
   ti,loczrama = <1>;
  };

  mcu_r5fss0_core1: r5f@41400000 {
   compatible = "ti,j7200-r5f";
   reg = <0x41400000 0x00008000>,
         <0x41410000 0x00008000>;
   reg-names = "atcm", "btcm";
   ti,sci = <&dmsc>;
   ti,sci-dev-id = <251>;
   ti,sci-proc-ids = <0x02 0xff>;
   resets = <&k3_reset 251 1>;
   firmware-name = "j7200-mcu-r5f0_1-fw";
   ti,atcm-enable = <1>;
   ti,btcm-enable = <1>;
   ti,loczrama = <1>;
  };
 };

 mcu_crypto: crypto@40900000 {
  compatible = "ti,j721e-sa2ul";
  reg = <0x00 0x40900000 0x00 0x1200>;
  power-domains = <&k3_pds 265 0>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
  dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
         <&mcu_udmap 0x7503>;
  dma-names = "tx", "rx1", "rx2";

  rng: rng@40910000 {
   compatible = "inside-secure,safexcel-eip76";
   reg = <0x00 0x40910000 0x00 0x7d>;
   interrupts = <0 945 4>;
   status = "disabled";
  };
 };

 wkup_vtm0: temperature-sensor@42040000 {
  compatible = "ti,j7200-vtm";
  reg = <0x00 0x42040000 0x00 0x350>,
        <0x00 0x42050000 0x00 0x350>;
  power-domains = <&k3_pds 154 1>;
  #thermal-sensor-cells = <1>;
 };

 mcu_esm: esm@40800000 {
  compatible = "ti,j721e-esm";
  reg = <0x00 0x40800000 0x00 0x1000>;
  ti,esm-pins = <95>;
  bootph-pre-ram;
 };

 mcu_mcan0: can@40528000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x40528000 0x00 0x200>,
        <0x00 0x40500000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 172 1>;
  clocks = <&k3_clks 172 0>, <&k3_clks 172 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 832 4>,
        <0 833 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };

 mcu_mcan1: can@40568000 {
  compatible = "bosch,m_can";
  reg = <0x00 0x40568000 0x00 0x200>,
        <0x00 0x40540000 0x00 0x8000>;
  reg-names = "m_can", "message_ram";
  power-domains = <&k3_pds 173 1>;
  clocks = <&k3_clks 173 0>, <&k3_clks 173 2>;
  clock-names = "hclk", "cclk";
  interrupts = <0 835 4>,
        <0 836 4>;
  interrupt-names = "int0", "int1";
  bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
  status = "disabled";
 };
};
# 312 "arch/arm64/boot/dts/company_name/custom-board.dts" 2

&wkup_pmx0 {
 fram_pins_default: fram-default-pins {
  pinctrl-single,pins = <
   (((0x0) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (0))
   (((0x2c) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (0))
   (((0xc) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0x10) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0x14) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0x18) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0x8) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0x4) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
  >;
 };
};

&wkup_pmx2 {
 pmic_i2c0_pins_default: pmic-i2c0-default-pins {
   pinctrl-single,pins = <
   (((0x98) & 0x1fff)) ((((1 << (18)) | (1 << (17) | (0 << (16))))) | (0))
   (((0x9c) & 0x1fff)) ((((1 << (18)) | (1 << (17) | (0 << (16))))) | (0))
  >;
 };

 mcu_uart0_pins_default: mcu-uart0-default-pins {
  pinctrl-single,pins = <
   (((0x94) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0x88) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (0))
  >;
 };

 ethernet0_pins_default: ethernet0-pins_default-pins {
  pinctrl-single,pins = <
   (((0x00) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (1))
   (((0x04) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (1))
   (((0x10) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (1))
   (((0x14) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (1))
   (((0x18) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (1))
   (((0x1c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (1))
   (((0x28) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (1))
   (((0x2c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (1))
  >;
 };

 sseg_led_pins_default: sseg-led-pins-default {
  pinctrl-single,pins = <
   (((0x64) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0x68) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0x6c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0x70) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0x74) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0x78) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0x7c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
  >;
 };

 emmc_access_mon_pins_default: emmc-access-mon-pins-default {
  pinctrl-single,pins = <
   (((0x80) & 0x1fff)) ((((0 << (18)) | (1 << (17) | (0 << (16))))) | (7))
  >;
 };

 status_ctrl_pins_default: status-ctrl-pins-default {
  pinctrl-single,pins = <
   (((0x44) & 0x1fff)) ((((0 << (18)) | (1 << (17) | (0 << (16))))) | (7))
   (((0x48) & 0x1fff)) ((((0 << (18)) | (0 << (17) | (0 << (16))))) | (7))
   (((0x4c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
  >;
 };

 dp83822_mdio_pins_default: dp83822-mdio-default-pins {
  pinctrl-single,pins = <
   (((0x34) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (0))
   (((0x30) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
  >;
 };

 mcu_clkout_pins_default: mcu-clkout-default-pins {
  pinctrl-single,pins = <
   (((0x83) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (6))
  >;
 };
};

&main_pmx0 {
 fan_sensor_pins_default: fan-sensor-default-pins {
  pinctrl-single,pins = <
   (((0xdc) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
  >;
 };

 gpio0_pins_default: gpio0-default-pins {
  pinctrl-single,pins = <
   (((0x4) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0x8) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0xc) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0x1c) & 0x1fff)) ((((0 << (18)) | (0 << (17) | (0 << (16))))) | (7))
   (((0x20) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
   (((0xac) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
  >;
 };

 ioexpander_i2c0_pins_default: ioexpander-i2c0-default-pins {
  pinctrl-single,pins = <
   (((0xd4) & 0x1fff)) ((((1 << (18)) | (1 << (17) | (0 << (16))))) | (0))
   (((0xd8) & 0x1fff)) ((((1 << (18)) | (1 << (17) | (0 << (16))))) | (0))
  >;
 };

 dp83867_mdio_pins_default: dp83867-mdio-default-pins {
  pinctrl-single,pins = <
   (((0xa8) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (5))
   (((0xa4) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (5))
  >;
 };

 debug_uart0_pins_default: debug-uart0-default-pins {
  pinctrl-single,pins = <
   (((0xb0) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xb4) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (0))
  >;
 };

 rs485_uart1_pins_default: rs485-uart1-default-pins {
  pinctrl-single,pins = <
   (((0xb8) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xbc) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xcc) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (1))
  >;
 };

 microsd_mmc1_pins_default: microsd-mmc1-default-pins {
  pinctrl-single,pins = <
   (((0x104) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0x100) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xfc) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xf8) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xf4) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xf0) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xec) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (0))
   (((0xe4) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (8))
  >;
 };

 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
  pinctrl-single,pins = <
   (((0xd0) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (7))
  >;
 };

 usb_ether_pins_default: usb-ether-default-pins {
  pinctrl-single,pins = <
   (((0x4c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x50) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x54) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x58) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x48) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x5c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x60) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x64) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x68) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x6c) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x74) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x70) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
  >;
 };

 ethernet_pins_default: ethernet-default-pins {
  pinctrl-single,pins = <
   (((0x7c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x80) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x84) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x88) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x78) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x8c) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (4))
   (((0x90) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x94) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x98) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x9c) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0x28) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
   (((0xa0) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (4))
  >;
 };

 system1_pins_default: system1-default-pins {
  pinctrl-single,pins = <
   (((0x108) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (0))
  >;
 };


};

&main_pmx1 {
 gpio1_pins_default: gpio1-default-pins {
  pinctrl-single,pins = <
   (((0x08) & 0x1fff)) ((((1 << (18)) | (1 << (16)))) | (7))
  >;
 };

 main_usbss0_pins_default: main-usbss0-default-pins {
  pinctrl-single,pins = <
   (((0x04) & 0x1fff)) ((((0 << (18)) | (1 << (16)))) | (0))
  >;
 };
};

&mailbox0_cluster0 {
 status = "disable";
};

&mailbox0_cluster1 {
 status = "disable";
};

&mcu_r5fss0 {
 status = "disable";
};

&main_i2c0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&ioexpander_i2c0_pins_default>;
 clock-frequency = <400000>;
};

&wkup_i2c0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&pmic_i2c0_pins_default>;
 clock-frequency = <400000>;

 tps659414: pmic@48 {
  compatible = "ti,tps6594-q1";
  reg = <0x48>;
  system-power-controller;
  interrupt-parent = <&wkup_gpio0>;
  interrupts = <84 2>;
  gpio-controller;
  #gpio-cells = <2>;
  ti,primary-pmic;
  buck1-supply = <&vsys_3v3>;
  buck2-supply = <&vsys_3v3>;
  buck3-supply = <&vsys_3v3>;
  buck4-supply = <&vsys_3v3>;
  buck5-supply = <&vsys_3v3>;
  ldo1-supply = <&vsys_3v3>;
  ldo2-supply = <&vsys_3v3>;
  ldo3-supply = <&vsys_3v3>;
  ldo4-supply = <&vsys_3v3>;

  regulators {
   bucka1: buck1 {
    regulator-name = "vda_mcu_1v8";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-boot-on;
    regulator-always-on;
   };

   bucka2: buck2 {
    regulator-name = "vdd_mcuio_1v8";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-boot-on;
    regulator-always-on;
   };

   bucka3: buck3 {
    regulator-name = "vdd_mcu_0v85";
    regulator-min-microvolt = <850000>;
    regulator-max-microvolt = <850000>;
    regulator-boot-on;
    regulator-always-on;
   };

   bucka4: buck4 {
    regulator-name = "vdd_ddr_1v1";
    regulator-min-microvolt = <1100000>;
    regulator-max-microvolt = <1100000>;
    regulator-boot-on;
    regulator-always-on;
   };

   bucka5: buck5 {
    regulator-name = "vdd_phyio_1v8";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldoa1: ldo1 {
    regulator-name = "vdd1_lpddr4_1v8";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldoa2: ldo2 {
    regulator-name = "vda_dll_0v8";
    regulator-min-microvolt = <800000>;
    regulator-max-microvolt = <800000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldoa3: ldo3 {
    regulator-name = "vdd_wk_0v8";
    regulator-min-microvolt = <800000>;
    regulator-max-microvolt = <800000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldoa4: ldo4 {
    regulator-name = "vda_pll_1v8";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-boot-on;
    regulator-always-on;
   };
  };
 };

 lp876441: pmic@4c {
  compatible = "ti,lp8764-q1";
  reg = <0x4c>;
  system-power-controller;
  interrupt-parent = <&wkup_gpio0>;
  interrupts = <84 2>;
  gpio-controller;
  #gpio-cells = <2>;
  buck1-supply = <&vsys_3v3>;
  buck2-supply = <&vsys_3v3>;
  buck3-supply = <&vsys_3v3>;
  buck4-supply = <&vsys_3v3>;

  regulators: regulators {
   buckb1: buck1 {
    regulator-name = "vdd_cpu_avs";
    regulator-min-microvolt = <600000>;
    regulator-max-microvolt = <900000>;
    regulator-always-on;
    regulator-boot-on;
    bootph-pre-ram;
   };

   buckb2: buck2 {
    regulator-name = "vdd_ram_0v85";
    regulator-min-microvolt = <850000>;
    regulator-max-microvolt = <850000>;
    regulator-boot-on;
    regulator-always-on;
   };

   buckb3: buck3 {
    regulator-name = "vdd_core_0v85";
    regulator-min-microvolt = <850000>;
    regulator-max-microvolt = <850000>;
    regulator-boot-on;
    regulator-always-on;
   };

   buckb4: buck4 {
    regulator-name = "vdd_io_1v8";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-boot-on;
    regulator-always-on;
   };
  };
 };
};

&hbmc_mux {
 status = "disable";
};

&hbmc {
 status = "disable";
};

&ospi0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&fram_pins_default>;

 mb85rs4mt@0 {
  status = "okay";
  compatible = "jedec,spi-nor", "fujitsu,mb85rs4mt";
  reg = <0x0>;
  spi-tx-bus-width = <4>;
  spi-rx-bus-width = <4>;
  spi-max-frequency = <40000000>;
  cdns,tshsl-ns = <60>;
  cdns,tsd2d-ns = <60>;
  cdns,tchsh-ns = <60>;
  cdns,tslch-ns = <60>;
  cdns,read-delay = <4>;

  partitions {
   compatible = "fixed-partitions";
   #address-cells = <1>;
   #size-cells = <1>;

   partition@0 {
    label = "fram.data";
    reg = <0x00000000 0x000080000>;
   };
  };
 };
};

&mcu_uart0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&mcu_uart0_pins_default>;
};

&main_uart0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&debug_uart0_pins_default>;
};

&main_uart1 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&rs485_uart1_pins_default>;
 rs485-rts-active-low;
 linux,rs485-enabled-at-boot-time;
};

&main_gpio0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&gpio0_pins_default>,
    <&gpio1_pins_default>;
};

&wkup_gpio0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&sseg_led_pins_default>, <&status_ctrl_pins_default>;
};

&mcu_cpsw {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&ethernet0_pins_default>, <&dp83822_mdio_pins_default>;
};

&davinci_mdio {
 status = "okay";
 phy0: ethernet-phy@0 {
  reg = <0>;
  rx-internal-delay-ps = <1>;
  tx-internal-delay-ps = <1>;
 };
};

&cpsw_port1 {
 status = "okay";
 phy-mode = "rmii";
 phy-handle = <&phy0>;
};

&main_sdhci0 {

 status = "okay";
 non-removable;
 ti,driver-strength-ohm = <50>;
 disable-wp;
};

&main_sdhci1 {

 status = "okay";
 pinctrl-0 = <&microsd_mmc1_pins_default>;
 pinctrl-names = "default";
 vmmc-supply = <&vdd_mmc1>;
 vqmmc-supply = <&vdd_sd_dv>;
 ti,driver-strength-ohm = <50>;
 disable-wp;
};

&serdes_ln_ctrl {
 idle-states = <0x3>, <0x3>,
        <0x3>, <0x2>;
};

&usb_serdes_mux {
 idle-states = <1>;
};

&usbss0 {
 pinctrl-names = "default";
 pinctrl-0 = <&main_usbss0_pins_default>;
 ti,vbus-divider;
};

&usb0 {
 dr_mode = "host";
 maximum-speed = "super-speed";
 phys = <&serdes0_usb_link>;
 phy-names = "cdns3,usb3-phy";
};

&tscadc0 {
 status = "okay";
 adc {
  ti,adc-channels = <0>;
 };
};

&serdes0 {
 status = "okay";
 serdes0_usb_link: phy@2 {
  status = "okay";
  reg = <3>;
  cdns,num-lanes = <1>;
  #phy-cells = <0>;
  cdns,phy-type = <4>;
  resets = <&serdes_wiz0 4>;
 };
};

&cpsw0 {
 status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&ethernet_pins_default>, <&usb_ether_pins_default>, <&dp83867_mdio_pins_default>;
};

&cpsw5g_mdio {
 status = "okay";
 cpsw5g_phy0: ethernet-phy@0 {
  reg = <0>;
  ti,rx-internal-delay = <0x7>;
  ti,fifo-depth = <0x01>;
  ti,min-output-impedance;
 };
};

&cpsw0_port2 {
 status = "okay";
 phy-mode = "rgmii-rxid";
 phy-handle = <&cpsw5g_phy0>;
 phys = <&cpsw0_phy_gmii_sel 2>;
};

&cpsw0_port3 {
 status = "okay";
 phy-mode = "rgmii-rxid";
 phys = <&cpsw0_phy_gmii_sel 3>;
 fixed-link {
  speed = <1000>;
  full-duplex;
    };
};

0x70 in wkup_pmx2 is WKUP_GPIO0_6(C14), but it is not used except for sseg_led_pins_default.

WKUP_GPIO0_6 changes when the following is output to the console.

Starting kernel ...

I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled

Are there any configuration files other than the device tree that could affect this timing?

Regards,

mizutani

0 Keerthy J 9 months ago in reply to user4852186

TI__Guru**** 165090 points

Hello,

Yes. The remote cores like the R5Fs can be accessing. The firmware running on them can potentially be changing the direction.

Can you rename /lib/firmware in your rootfs to say /lib/firmware-backup

Then try to boot. This will avoid the default firmware loading on to R5Fs.

Best regards,

Keerthy

0 user4852186 9 months ago in reply to Keerthy J

Intellectual 340 points

Hi,

We renamed /lib/firmware to /lib/firmware-backup in the root filesystem.

However, this phenomenon still occurs.

Are there any other possible factors?

Regards,

mizutani

0 Keerthy J 9 months ago in reply to user4852186

TI__Guru**** 165090 points

Hello mizutani,

Please share the complete boot logs to double check if the firmware is not loaded. Its either Linux or the remote core firmwares that can write registers.

- Keerthy

0 user4852186 9 months ago in reply to Keerthy J

Intellectual 340 points

Hi,

The boot log is shown below.

############################### 7seg='8' ###############################
U-Boot SPL 2024.04 (Feb 10 2025 - 13:32:14 +0900)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

############################### 7seg='1' ###############################

NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024
I/TC:
I/TC: OP-TEE version: 4.2.0-dev (gcc version 13.3.0 (GCC)) #1 Fri Apr 12 09:51:21 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04 (Feb 10 2025 - 13:32:12 +0900)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted

############################### 7seg='2' ###############################

U-Boot 2024.04 (Feb 10 2025 - 13:32:12 +0900)

SoC:   J7200 SR2.0 GP
Model: COMPANY_NAME CUSTOM_BOARD
DRAM:  2 GiB (effective 4 GiB)
Core:  85 devices, 30 uclasses, devicetree: separate
MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@2800000
Out:   serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@c000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00294104 Ports:4
Net:   eth1: ethernet@c000000port@2
395 bytes read in 12 ms (31.3 KiB/s)
Loaded environment from MicroSD
Hit any key to stop autoboot:  0

############################### 7seg='3' ###############################

k3-navss-ringacc ringacc@3c000000: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211
k3-navss-ringacc ringacc@3c000000: dma-ring-reset-quirk: disabled
am65_cpsw_nuss_port ethernet@c000000port@2: K3 CPSW: rflow_id_base: 4
ethernet@c000000port@2 Waiting for PHY auto negotiation to complete... done
link up on port 2, speed 1000, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 192.168.22.192 (1261 ms)
Using ethernet@c000000port@2 device
TFTP from server 192.168.22.250; our IP address is 192.168.22.192
Filename 'Image'.
Load address: 0x82000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #######################################################  0 Bytes
         2.1 MiB/s
done
Bytes transferred = 22575616 (1587a00 hex)
am65_cpsw_nuss_port ethernet@c000000port@2: K3 CPSW: rflow_id_base: 4
link up on port 2, speed 1000, full duplex
Using ethernet@c000000port@2 device
TFTP from server 192.168.22.250; our IP address is 192.168.22.192
Filename 'COMPANY_NAME-CUSTOM_BOARD.dtb'.
Load address: 0x88000000
Loading: ###############  0 Bytes
         1.9 MiB/s
done
Bytes transferred = 74078 (1215e hex)

############################### 7seg='4' ###############################

## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
Working FDT set to 88000000
   Loading Device Tree to 000000008ffea000, end 000000008ffff15d ... OK
Working FDT set to 8ffea000

Starting kernel ...

############################### 7seg='y' ############################### <= 7SEG_d(WKUP_GPIO0_6) lights up unintentionally

I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 6.6.32-rt32 (COMPANY_NAME@COMPANY_NAME) (aarch64-oe-linux-gcc (GCC) 13.3.0, GNU ld (GNU Binutils) 2.42.0.20240716) #0001 SMP PREEMPT_RT 2024/10/01
[    0.000000] Machine model: COMPANY_NAME CUSTOM_BOARD
[    0.000000] efi: UEFI not found.
[    0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000008ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x000000009fffffff]
[    0.000000]   node   0: [mem 0x00000000a0000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] cma: Reserved 32 MiB at 0x00000000fe000000 on node -1
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.4
[    0.000000] percpu: Embedded 29 pages/cpu s81344 r8192 d29248 u118784
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: Spectre-BHB
[    0.000000] CPU features: kernel page table isolation disabled by kernel configuration
[    0.000000] CPU features: detected: ARM erratum 1742098
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] alternatives: applying boot alternatives
[    0.000000] Kernel command line: console=ttyS2,115200n8 root=/dev/nfs nfsroot=192.168.22.250:/home/COMPANY_NAME/sdk/targetNFS,nolock,v3,tcp,rsize=4096,wsize=4096 ro ip=dhcp COMPANY_NAME_BOOTDEV=microsd COMPANY_NAME_BOOTMODE=nfs COMPANY_NAME_BOOTREV=0.0.0.1
[    0.000000] Unknown kernel command line parameters "COMPANY_NAME_BOOTDEV=microsd COMPANY_NAME_BOOTMODE=nfs COMPANY_NAME_BOOTREV=0.0.0.1", will be passed to user space.
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1032192
[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[    0.000000] software IO TLB: area num 2.
[    0.000000] software IO TLB: mapped [mem 0x00000000fa000000-0x00000000fe000000] (64MB)
[    0.000000] Memory: 3975764K/4194304K available (11072K kernel code, 2142K rwdata, 4308K rodata, 4416K init, 436K bss, 185772K reserved, 32768K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] ftrace: allocating 40019 entries in 157 pages
[    0.000000] ftrace: allocated 157 pages with 5 groups
[    0.000000] trace event string verifier disabled
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[    0.000000] rcu:     RCU_SOFTIRQ processing moved to rcuc kthreads.
[    0.000000]  No expedited grace period (rcu_normal_after_boot).
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000]  Rude variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GICv3: GICv3 features: 16 PPIs
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @880800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x00000008801a0000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008801b0000
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.000125] Console: colour dummy device 80x25
[    0.000156] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=200000)
[    0.000161] pid_max: default: 32768 minimum: 301
[    0.000192] LSM: initializing lsm=capability,integrity
[    0.000257] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.000274] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.001203] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
[    0.001250] RCU Tasks Rude: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1.
[    0.001398] rcu: Hierarchical SRCU implementation.
[    0.001401] rcu:     Max phase no-delay instances is 400.
[    0.001675] Platform MSI: msi-controller@1820000 domain created
[    0.001776] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.001812] EFI services will not be available.
[    0.001904] smp: Bringing up secondary CPUs ...
[    0.010587] Detected PIPT I-cache on CPU1
[    0.010631] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.010646] GICv3: CPU1: using allocated LPI pending table @0x00000008801c0000
[    0.010677] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.010752] smp: Brought up 1 node, 2 CPUs
[    0.010757] SMP: Total of 2 processors activated.
[    0.010759] CPU features: detected: 32-bit EL0 Support
[    0.010762] CPU features: detected: CRC32 instructions
[    0.010794] CPU: All CPU(s) started at EL2
[    0.010796] alternatives: applying system-wide alternatives
[    0.011547] devtmpfs: initialized
[    0.033162] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
[    0.033174] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
[    0.033815] pinctrl core: initialized pinctrl subsystem
[    0.034306] DMI not present or invalid.
[    0.034583] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.035862] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[    0.035991] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.036134] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.036173] audit: initializing netlink subsys (disabled)
[    0.036263] audit: type=2000 audit(0.036:1): state=initialized audit_enabled=0 res=1
[    0.036825] thermal_sys: Registered thermal governor 'step_wise'
[    0.037003] ASID allocator initialised with 65536 entries
[    0.059875] Modules: 27136 pages in range for non-PLT usage
[    0.059881] Modules: 518656 pages in range for PLT usage
[    0.060420] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    0.060426] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[    0.060429] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[    0.060431] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[    0.060434] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.060436] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[    0.060438] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[    0.060441] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[    0.061575] k3-chipinfo 43000014.chipid: Family:J7200 rev:SR2.0 JTAGID[0x1bb6d02f] Detected
[    0.062159] iommu: Default domain type: Translated
[    0.062164] iommu: DMA domain TLB invalidation policy: strict mode
[    0.062440] SCSI subsystem initialized
[    0.062690] usbcore: registered new interface driver usbfs
[    0.062733] usbcore: registered new interface driver hub
[    0.062772] usbcore: registered new device driver usb
[    0.063193] pps_core: LinuxPPS API ver. 1 registered
[    0.063196] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.063209] PTP clock support registered
[    0.063373] EDAC MC: Ver: 3.0.0
[    0.063825] scmi_core: SCMI protocol bus registered
[    0.064122] FPGA manager framework
[    0.065515] clocksource: Switched to clocksource arch_sys_counter
[    0.065732] VFS: Disk quotas dquot_6.6.0
[    0.065749] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.074124] NET: Registered PF_INET protocol family
[    0.074416] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.075940] tcp_listen_portaddr_hash hash table entries: 2048 (order: 4, 81920 bytes, linear)
[    0.076001] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.076008] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.076238] TCP bind hash table entries: 32768 (order: 9, 2621440 bytes, linear)
[    0.079743] TCP: Hash tables configured (established 32768 bind 32768)
[    0.079926] UDP hash table entries: 2048 (order: 5, 196608 bytes, linear)
[    0.080132] UDP-Lite hash table entries: 2048 (order: 5, 196608 bytes, linear)
[    0.080505] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.080881] RPC: Registered named UNIX socket transport module.
[    0.080886] RPC: Registered udp transport module.
[    0.080889] RPC: Registered tcp transport module.
[    0.080891] RPC: Registered tcp-with-tls transport module.
[    0.080893] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.080904] PCI: CLS 0 bytes, default 64
[    0.369922] Initialise system trusted keyrings
[    0.370088] workingset: timestamp_bits=62 max_order=20 bucket_order=0
[    0.370365] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.370586] NFS: Registering the id_resolver key type
[    0.370603] Key type id_resolver registered
[    0.370606] Key type id_legacy registered
[    0.370619] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.370623] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.384606] Key type asymmetric registered
[    0.384611] Asymmetric key parser 'x509' registered
[    0.384655] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.384659] io scheduler mq-deadline registered
[    0.384662] io scheduler kyber registered
[    0.384675] io scheduler bfq registered
[    0.388208] pinctrl-single 4301c000.pinctrl: 13 pins, size 52
[    0.388432] pinctrl-single 4301c038.pinctrl: 2 pins, size 8
[    0.388602] pinctrl-single 4301c068.pinctrl: 59 pins, size 236
[    0.389129] pinctrl-single 4301c174.pinctrl: 8 pins, size 32
[    0.389318] pinctrl-single 104200.pinctrl: 20 pins, size 80
[    0.389432] pinctrl-single 104280.pinctrl: 8 pins, size 32
[    0.389601] pinctrl-single 11c000.pinctrl: 67 pins, size 268
[    0.390295] pinctrl-single 11c11c.pinctrl: 3 pins, size 12
[    0.397757] Serial: 8250/16550 driver, 12 ports, IRQ sharing enabled
[    0.411863] loop: module loaded
[    0.412816] megasas: 07.725.01.00-rc1
[    0.418010] tun: Universal TUN/TAP device driver, 1.6
[    0.418783] VFIO - User Level meta-driver version: 0.3
[    0.419967] usbcore: registered new interface driver usb-storage
[    0.420618] i2c_dev: i2c /dev entries driver
[    0.421407] sdhci: Secure Digital Host Controller Interface driver
[    0.421410] sdhci: Copyright(c) Pierre Ossman
[    0.421611] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.422391] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.423762] optee: probing for conduit method.
[    0.423779] optee: revision 4.2 (12d7c4ee)
[    0.440363] optee: dynamic shared memory is enabled
[    0.440871] random: crng init done
[    0.440927] optee: initialized driver
[    0.442351] NET: Registered PF_PACKET protocol family
[    0.442410] Key type dns_resolver registered
[    0.458554] Loading compiled-in X.509 certificates
[    0.476313] ti-sci 44083000.system-controller: ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[    0.566850] omap_i2c 42120000.i2c: bus 0 rev0.12 at 400 kHz
[    0.567816] omap_i2c 2000000.i2c: bus 1 rev0.12 at 400 kHz
[    0.568151] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 137 domain created
[    0.568292] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 131 domain created
[    0.568420] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 213 domain created
[    0.568669] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 209 created
[    0.573631] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
[    0.573641] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    0.573644] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[    0.584934] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211
[    0.584944] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    0.584946] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[    0.586176] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 266, base_baud = 6000000) is a 8250
[    0.587694] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 267, base_baud = 3000000) is a 8250
[    0.587803] printk: console [ttyS2] enabled
[    0.589281] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 268, base_baud = 3000000) is a 8250
[    0.591454] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[    0.625525] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    0.628956] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83822
[    0.628996] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    0.629170] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    0.629174] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    0.631432] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    0.665524] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    0.668129] davinci_mdio c000f00.mdio: phy[0]: device c000f00.mdio:00, driver TI DP83867
[    0.668163] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
[    0.668716] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    0.668728] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
[    0.668731] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    0.671359] mmc0: CQHCI version 5.10
[    0.712229] tps6594-rtc tps6594-rtc.4.auto: registered as rtc0
[    0.713135] tps6594-rtc tps6594-rtc.4.auto: setting system clock to 2024-12-28T00:09:50 UTC (1735344590)
[    0.714050] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    0.726122] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[    0.731870] ti-udma 31150000.dma-controller: Channels: 50 (tchan: 25, rchan: 25, gp-rflow: 8)
[    0.739578] spi-nor spi0.0: unrecognized JEDEC id bytes: 08 fe 53 0b ff ff
[    0.740291] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[    0.774525] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    0.778098] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83822
[    0.778135] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    0.778309] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    0.778313] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    0.816631] mmc0: Command Queue Engine enabled
[    0.816640] mmc0: new HS400 MMC card at address 0001
[    0.817266] mmcblk0: mmc0:0001 G1M15L 29.6 GiB
[    0.820609]  mmcblk0: p1 p2 p3 p4 < p5 p6 p7 p8 p9 >
[    0.823101] mmcblk0boot0: mmc0:0001 G1M15L 31.5 MiB
[    0.825046] mmcblk0boot1: mmc0:0001 G1M15L 31.5 MiB
[    0.826750] mmcblk0rpmb: mmc0:0001 G1M15L 4.00 MiB, chardev (240:0)
[    0.942191] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    0.948162] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[    0.982526] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    0.985173] davinci_mdio c000f00.mdio: phy[0]: device c000f00.mdio:00, driver TI DP83867
[    0.985207] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
[    0.985798] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    0.985812] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
[    0.985815] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    1.148665] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 60
[    1.158332] mmc1: CQHCI version 5.10
[    1.202665] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    1.213021] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [TI DP83822] (irq=POLL)
[    1.213032] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rmii link mode
[    1.231241] am65-cpsw-nuss c000000.ethernet eth1: PHY [c000f00.mdio:00] driver [TI DP83867] (irq=POLL)
[    1.231253] am65-cpsw-nuss c000000.ethernet eth1: configuring for phy/rgmii-rxid link mode
[    1.240448] am65-cpsw-nuss c000000.ethernet eth2: configuring for fixed/rgmii-rxid link mode
[    1.240480] am65-cpsw-nuss c000000.ethernet eth2: Link is Up - 1Gbps/Full - flow control off
[    1.256527] Sending DHCP requests .
[    1.364195] sdhci-am654 4fb0000.mmc: No passing ITAPDLY, return 0
[    1.364231] mmc1: new ultra high speed DDR50 SDHC card at address 0001
[    1.364905] mmcblk1: mmc1:0001 0004G 3.71 GiB
[    1.368563]  mmcblk1: p1 p2
[    4.019521] .
[    5.344750] am65-cpsw-nuss c000000.ethernet eth1: Link is Up - 1Gbps/Full - flow control rx/tx
[    8.855520] ., OK
[    8.861460] IP-Config: Got DHCP answer from 192.168.22.1, my address is 192.168.22.192
[    8.861476] IP-Config: Complete:
[    8.861478]      device=eth1, hwaddr=00:e0:4e:30:00:01, ipaddr=192.168.22.192, mask=255.255.255.0, gw=192.168.22.1
[    8.861482]      host=192.168.22.192, domain=, nis-domain=(none)
[    8.861485]      bootserver=0.0.0.0, rootserver=192.168.22.250, rootpath=
[    8.861487]      nameserver0=192.168.22.1
    8.883185] am65-cpsw-nuss c000000.ethernet eth2: Link is Down
[    8.883316] clk: Disabling unused clocks
[    8.940709] VFS: Mounted root (nfs filesystem) readonly on device 0:22.
[    8.941778] devtmpfs: mounted
[    8.945922] Freeing unused kernel memory: 4416K
[    8.946040] Run /sbin/init as init process
[    9.214074] NET: Registered PF_INET6 protocol family
[    9.222055] Segment Routing with IPv6
[    9.222093] In-situ OAM (IOAM) with IPv6
[    9.243065] systemd[1]: systemd 255.4^ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -TPM2 -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
[    9.243826] systemd[1]: Detected architecture arm64.

Welcome to Arago 2023.10!

*The status of the 7-segment LED is being appended to the log. (Appended content: ############ 7seg='x' ##############)

Regards,

mizutani

0 Keerthy J 9 months ago in reply to user4852186

TI__Guru**** 165090 points

Hi,

############################### 7seg='8' ###############################
U-Boot SPL 2024.04 (Feb 10 2025 - 13:32:14 +0900)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

############################### 7seg='1' ###############################

NOTICE: BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE: BL31: Built : 16:09:05, Feb 9 2024
I/TC:
I/TC: OP-TEE version: 4.2.0-dev (gcc version 13.3.0 (GCC)) #1 Fri Apr 12 09:51:21 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04 (Feb 10 2025 - 13:32:12 +0900)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted

############################### 7seg='2' ###############################

U-Boot 2024.04 (Feb 10 2025 - 13:32:12 +0900)

SoC: J7200 SR2.0 GP
Model: COMPANY_NAME CUSTOM_BOARD
DRAM: 2 GiB (effective 4 GiB)
Core: 85 devices, 30 uclasses, devicetree: separate
MMC: mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from nowhere... OK
In: serial@2800000
Out: serial@2800000
Out: serial@2800000
Err: serial@2800000
am65_cpsw_nuss ethernet@c000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00294104 Ports:4
Net: eth1: ethernet@c000000port@2
395 bytes read in 12 ms (31.3 KiB/s)
Loaded environment from MicroSD
Hit any key to stop autoboot: 0

############################### 7seg='3' ###############################

k3-navss-ringacc ringacc@3c000000: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211
k3-navss-ringacc ringacc@3c000000: dma-ring-reset-quirk: disabled
am65_cpsw_nuss_port ethernet@c000000port@2: K3 CPSW: rflow_id_base: 4
ethernet@c000000port@2 Waiting for PHY auto negotiation to complete... done
link up on port 2, speed 1000, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 192.168.22.192 (1261 ms)
Using ethernet@c000000port@2 device
TFTP from server 192.168.22.250; our IP address is 192.168.22.192
Filename 'Image'.
Load address: 0x82000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
####################################################### 0 Bytes
2.1 MiB/s
done
Bytes transferred = 22575616 (1587a00 hex)
am65_cpsw_nuss_port ethernet@c000000port@2: K3 CPSW: rflow_id_base: 4
link up on port 2, speed 1000, full duplex
Using ethernet@c000000port@2 device
TFTP from server 192.168.22.250; our IP address is 192.168.22.192
Filename 'COMPANY_NAME-CUSTOM_BOARD.dtb'.
Load address: 0x88000000
Loading: ############### 0 Bytes
1.9 MiB/s
done
Bytes transferred = 74078 (1215e hex)

############################### 7seg='4' ###############################

## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Working FDT set to 88000000
Loading Device Tree to 000000008ffea000, end 000000008ffff15d ... OK
Working FDT set to 8ffea000

Starting kernel ...

############################### 7seg='y' ############################### <= 7SEG_d(WKUP_GPIO0_6) lights up unintentionally

This is even before kernel starts executing or it was just a place that you added? I see that U-Boot is not loading any remote core firmware.
Can you tell me precisely at what point of boot the LED is lit up unintentionally?

- Keerthy

0 user4852186 9 months ago in reply to Keerthy J

Intellectual 340 points

Hi,

Sorry. I'm not sure of the exact timing because I'm checking the LED visually.

What methods are available to accurately determine timing?
Is it possible to set a breakpoint at the kernel startup timing via JTAG (CCS)?

Regards,

mizutani

0 Keerthy J 9 months ago in reply to user4852186

TI__Guru**** 165090 points

Hi mizutani,

Till now what I have understood is that it is fine till U-Boot right? If you read register in U-Boot is that set correctly?

Regards,

Keerthy

0 user4852186 9 months ago in reply to Keerthy J

Intellectual 340 points

Hi,

I have confirmed that it works as intended up to u-boot. I also checked it with CCS and the register values were correct.

Regards,

mizutani

0 Keerthy J 9 months ago in reply to user4852186

TI__Guru**** 165090 points

Hi mizutani.

Can you add an infinite loop here:

git diff drivers/gpio/gpio-davinci.c 
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index 8c033e8cf3c9..fe947919f326 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -158,7 +158,9 @@ static int davinci_gpio_probe(struct platform_device *pdev)
        unsigned int ngpio, nbank, nirq, gpio_unbanked;
        struct davinci_gpio_controller *chips;
        struct device *dev = &pdev->dev;
+       volatile int vol = 1;
 
+       while(vol);
        /*
         * The gpio banks conceptually expose a segmented bitmap,
         * and "ngpio" is one more than the largest zero-based

You can attach the CCS and read out the reg value. Set a write breakpoint on the MMR for the WKUP_GPIO.
You could try that and that should be the simplest way to figure what is writing.

- Keerthy

0 user4852186 9 months ago in reply to Keerthy J

Intellectual 340 points

Hi,

By adding an infinite loop, we were able to determine where the LED was being rewritten.

The issue was prevented by commenting out “fdt_ret = ft_board_setup(blob, gd->bd);” in board-support/ti-u-boot-2024.04+git/boot/image-fdt.c.

int image_setup_libfdt(struct bootm_headers *images, void *blob,
		       struct lmb *lmb)
{
	ulong *initrd_start = &images->initrd_start;
	ulong *initrd_end = &images->initrd_end;
	int ret, fdt_ret, of_size;
	
	...
	
	
#if IS_ENABLED(CONFIG_CMD_PSTORE)
	/* Append PStore configuration */
	fdt_fixup_pstore(blob);
#endif
	if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) {
		const char *skip_board_fixup;

		skip_board_fixup = env_get("skip_board_fixup");
		if (skip_board_fixup && ((int)simple_strtol(skip_board_fixup, NULL, 10) == 1)) {
			printf("skip board fdt fixup\n");
		} else {
			fdt_ret = ft_board_setup(blob, gd->bd);    <===
			if (fdt_ret) {
				printf("ERROR: board-specific fdt fixup failed: %s\n",
				       fdt_strerror(fdt_ret));
				goto err;
			}
		}
	}	
	if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) {
		fdt_ret = ft_system_setup(blob, gd->bd);

Do you know why commenting out "ft_board_setup" stops this from happening?

Regarding the countermeasure, which is better: commenting out "ft_board_setup" or setting "CONFIG_OF_BOARD_SETUP=n"?

Regards,

mizutani

+1 Keerthy J 9 months ago in reply to user4852186

TI__Guru**** 165090 points

Hi mizutani,

Thanks for the information! This is a GPIO usage for selecting hyperbus.

If you do not have that requirement please comment out detect_enable_hyperflash.

That should take care of unintended GPIO changes.

Let me know.

Best Regards,
Keerthy

Processors

Processors forum

DRA821U: About WKUP_GPIO0_6