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TMS320VC5507: CVDD ripple noise tolerance

kenichiro sato
Prodigy 40 points
Part Number: TMS320VC5507


Tool/software:

I am using TMS320VC5507PGE.
I am using it with CVDD = 1.62 V (196.608 MHz).
16.384MHz is multiplied by 12 inside the DSP to get 196.608MHz.

(1) What is the allowable ripple for CVDD?
The following is stated for USBPLLVDD. Please provide a similar value for CVDD.
[†USB PLL is susceptible to power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10 MHz; 3% for 10 MHz to 100 MHz, and less than 5% for 100 MHz or greater.]

(2) Is it okay to use 1.60V for CVDD when using 196.608MHz?
Since it is 1.60V at 200MHz, would it be 1.58V at 196.608MHz?

(3) Based on a. through d. below, can we understand it as follows?
"When the noise level (or ripple level) exceeds CVDD±3%V, the DPLL inside the DSP malfunctions, and the multiplication frequency fluctuates. If it is within the range of CVDD±3%, it will not malfunction.
If it is within CVDD±3%, the noise frequency, impulse noise, and other noise shapes are not relevant.
This noise (ripple) tolerance changes depending on the DSP temperature and DSP pressure.
Noise (ripple) tolerance differs between individual DSPs."
=========================================================
When the 1.6V power supply noise is large,
a. The multiplied frequency of 196.608MHz drops by about -0.2%.
b. It is temperature dependent, and this phenomenon occurs when the DSP surface temperature is around 32.5°C.
c. This phenomenon also occurs when pressing or bending the DSP.
d. Even with the same noise level, there are some DSPs for which the phenomenon occurs and some for which it does not.
========================================================
Please answer questions (1) to (3) above.
Thank you in advance.

  • 0
    TI__Mastermind 22695 points

    Hi,

    (1)  The allowable ripple is as determined by the comment you mentioned.  Based on your using of 16.384MHz, yes, I agree that 3% is the maximum allowable ripple on CVDD.  Unfortunately, we don't have any data on what the tolerance is of the output of the PLL based on staying within the allowable ripple on CVDD, which I think is the ultimate root cause here.

    (2)  Yes, using 1.60V for 196.608MHz is fine.  Per the datasheet, at CVDD=1.6V (200 MHz), the Recommended Operating Conditions for USBPLLVDD is 1.55 to 1.65V.  You should stay within this range (including the 3% ripple) and you can run the device at 196.608MHz.

    (3)  Unfortunately, it is not quite so exact as "stay within this range and no fluctuation; go out of range, there is fluctuation."  The way datasheets are written is that if you stay within the ranges defined by the Recommended Operating Conditions, then the result stays within the specified allowable range.  Fluctuations in temperature and voltage will ALWAYS have some impact on the output frequency of the PLL, but as long as those fluctuations stay within the allowable conditions, the resulting output stays within the allowable range.  As noted above, we don't specify in the datasheet what the output tolerance is of the PLL.  This means we don't have any data saying if the 0.2% shift in output is within the allowable range or not.  FYI, this is related to this other E2E post that you asked:  https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1457718/tms320vc5507-tms320vc5507-dpll-accuracy/5594700#5594700.  I have not forgotten about this post and am still trying to track down if there is any data we still have, but as mentioned on that thread, with the TMS320VC5507 device being marked as "No design support from TI available", it is quite challenging to get any data that is not in the datasheet.

    One additional question, have you swapped the DSPs around on the different boards to confirm the problem follows the DSP itself and not the board?

    Thanks,
    Mike