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SK-AM69: Controlling WKUP GPIOs at Main Domain processor.

Part Number: SK-AM69

Tool/software:

Hi, I'm currently working on SK-AM69 and I need to use a module which uses SPI.

I found out there are some GPIO pins that I can mux as SPI on 40-pin header.
And I want to control them on Linux(which runs at main domain) but they are WKUP domain GPIO.

Is there any way to control WKUP domain GPIO at Main domain?

  • Hi,

    You can do this. You can see the reference for wkup domain pinmux being controlled from linux at "arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi".

    Regards,
    Tanmay

  • Hi Tanmay,

    Thank you for the quick response.

    I checked out the mentioned file and I added these to device tree.

    &mcu_spi0 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcu_spi1_pins_default>;
    
    	spidev@0 {
    		compatible = "rohm,dh2228fv";
    		spi-max-frequency = <20000000>;
    		reg = <0>;
    	};
    };
    
    &wkup_pmx2 {
    	bootph-all;
    
    #if	1
    	mcu_spi1_pins_default: mcu_spi1-default-pins {
            pinctrl-single,pins = <
                J784S4_WKUP_IOPAD(0x038, PIN_INPUT, 0) /* (G38) MCU_SPI0_CLK */
                J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (F37) MCU_SPI0_CS0 */
                J784S4_WKUP_IOPAD(0x03c, PIN_INPUT, 0) /* (H36) MCU_SPI0_D0 */
                J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 0) /* (J38) MCU_SPI0_D1 */
            >;
        };
    #endif 
    }

    When I boot up the Linux kernel, it successfully probed and device path (/dev/spidev1.0) shows up.

    But when I try to test SPI communication through this device on userspace, the device freezes up and I need to force reboot it with reboot switch.

    I use (https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c) to test SPI communication.

    I find out that MCU_SPI1_* pins are connected to CPLD.
    Could this be causing the freeze?

    Regards,
    Minsoo

  • Hi,

    I found this FAQ for spidev. can you take a look at this and see if you are missing something. 

    I find out that MCU_SPI1_* pins are connected to CPLD.

    What is CPLD?

    Regards,
    Tanmay

  • Hi,

    I don't know much about the CPLD, all I know is that It is some kind of simplified FPGA.
    MCU_SPI1_* pins are connected into CPLD and 40-pin header at same time. 

    (AP)MCU_SPI1_* --> MCU_BOOTMODE_* --> CPLD and 40-pin header

    Regards,
    Minsoo

  • It seems like I had some mistake on the devicetree.
    I checked MOSI line through oscilloscope, and I successfully decode data that I sent on SK-AM69.

  • Thanks for the confirmation,

    Closing this ticket.

    Regards,
    Tanmay