I'm thinking to divide Oscillator(24MHz) into OSCIN and Sensor's VCLK.
- Please let me know how large input load capacity of OSCIN.
On the other part
I'm thinking to divide Sonsor's PCLK(24MHz) into VPCLKIN_0 and VPCLKIN_2.
- Please let me know how large input load capacity of VPCLKIN_0 and VPCLKIN_2.
I wanna use VPIF output (VP_DOUT0 - VP_DOUT7 and VPCLKOUT_2).
- It must be synchronized VPCLKIN_0 and VPCLKIN_2?
[Connection diagram]
---------------------
| [AM1806] |
Oscillator ------| OSCIN |
| | |
| | VPCLKIN_0 |----|
| | | |
| | VPCLKIN_2 |----|
| | | |
| --------------------- |
| |
| ---------------------- |
| | [Sensor] | |
--- VCLK -> PCLK -----
| |
----------------------