SK-AM62P-LP: Watchdog Driver Issue and DWWD/DWD Example Inquiry

Hello Debashis,

I am looking at your queries and you may expect reply in one or two days .

Regards,

Anil.

Hi Anil,
Thanks for informing we are waiting for your reply.

Hello Debashis,

The WDT is available on the SDL. Please look at the example below to configure WDT in MCU R5F.

The WDT is not able to make the AUTORESET SOC once the Watchdog is expired and users need to integrate the ESM module with the WDT to make the AUTORESET the SOC. The FAQ below explains the all implementation.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1283237/faq-am64x-am62x-how-to-reset-the-soc-when-wdt-timer-expires-in-am64x-and-am62x

C:\ti\mcu_plus_sdk_am62px_10_00_00_14\examples\sdl

If you want only the WDT example and ESM module separately, then follow the steps below.

The WDT is available on A53 core in AM62A devices and this driver integrates it into the AM62P MCU+SDK.

Update the make files to compile this driver and later call the WDT API's from the Application with the MCU RTI baseaddress.

Once this driver integration is done, take only the ESM module code from the sdl component and integrate it into the WDT Application.

I am sharing the links below to help you to integration of WDT in M4F core in AM64X devices and the same procedure is valued in AM62P devices as well. You can follow the same method as well.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1362747/am6442-wdt-on-m4f

Regards,

Anil.

Hi Anil,

I found that example and added this code for soc reset can you explain more in this?

/* Unlock CONTROL MMR registers */
         SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_WKUP, rstPartition);

         ctrl_addr = (volatile uint32_t *)(0x43018170);

         *ctrl_addr &= (~(1<<17));

         /* Lock CONTROL MMR registers */
         SOC_controlModuleLockMMR(SOC_DOMAIN_ID_WKUP, rstPartition);

RTI DWWD proper servicing test running. 
   Please wait for max 10000 ms. 

Timeout value is 327679
currout value is 33237226

/* Get current down counter */
        currentDownCounter = HW_RD_REG32(baseAddr + RTI_RTIDWDCNTR);
        DebugP_log("currout value is %ld\n",currentDownCounter);

Hello Debashis,

I am looking at your queries and you may expect reply in one or two days .

Regards,

Anil.

Debashis Mahanty said:

I found that example and added this code for soc reset can you explain more in this?

Hello Debashis,

With the above code change, we will be able to make the SOC reset with the  ESM module .

This bit will decide whether the SOC should Reset or not with the ESM module .

For the full details about the register, you can see the register description.

Debashis Mahanty said:

once the watchdog is started is it possible to disable it?  I think no 

Yes, WDT can't be disabled after the enableing .

Debashis Mahanty said:

So, I have tried using CCS to flash only the MCU. I didn't find an issue with the first attempt; it worked successfully, but on the next attempt, it gave the down count issue, something like this until I gave a power recycle to the board.

Please look at the FAQ below which helps you to debug all the WDT issues.

If the FAQ below is not helpful, I can help you. 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1414222/faq-am6442-watchdog-debug-and-configuration-guide-for-all-sitara-am6x-mpu-devices

Regards,

Anil.