AM62A7: AM62A7(speed U) DDR overclock to 3733MT/s

Fadong XUE Fadong XUE

Prodigy 160 points

Part Number: AM62A7
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hello,team

sdk：ti-processor-sdk-linux-edgeai-am62axx-evm-09_02_00_05 & mcu_plus_sdk_am62ax_09_02_00_38

Chip model：

Due to the performance requirements of the project, we need to increase the DDR frequency, we are currently attempting to overclock to speed V using AM62A7 (speed U). The SPL startup program can start normally, and the DDR rate after startup is 3733MT/s, as shown in the following figure:

However, when we use SBL stage1 to start the program and set the rate to 3733MT/s, TISCI will return an error when setting the DDR clock frequency. The following figure is the source code of SBL stage1. In the section of setting DDR rate, I have added some debugging information, including frequency and return status values:

When the rate is set to 3733MT/s, an error value of -1 is returned and the startup fails:

We tried other rates, such as changing it to 3730MT/s or 3734MT/s, and both were able to start successfully, with corresponding rates after startup,

We can directly change the clock frequency to 932999999 or 933000001, but just 933000000 will not work.

May I ask if TISCI has imposed a restriction on 3733MT/s?

Best regards,

XUE Fadong

6 months ago

0 JJD 6 months ago

TI__Guru* 85990 points

There is probably a software restriction on 3733MTs specifically, but really there should be a software restriction on any operation >3200MTs. The software is most likely reading the speed grade of the device and limiting the choice for 3733MTs

Note that you can overclock Speed Grade U devices for development purposes, but technically you should not operate a speed grade U devices >3200MTs

Regards,

James

0 Yogesh Siraswar 6 months ago in reply to JJD

TI__Mastermind 20675 points

Could you please share how you are changing frequency in case of SBL?

0 Fadong XUE Fadong XUE 6 months ago in reply to JJD

Prodigy 160 points

Hello,James:

Our product needs to be developed and tested based on 3733MT/s. Can you provide a method to lift the restriction.

Best regards,

XUE Fadong

0 Fadong XUE Fadong XUE 6 months ago in reply to Yogesh Siraswar

Prodigy 160 points

Hello,Yogesh:

case 3730MT/s、3733MT/s、3734MT/s：

We use the SysConfig tool to generate board-d drReginit. h, use the new board-d drReginit. h, and recompile SBL.

case 932999999、933000001：

We directly modify the frequency in the SBL source code and recompile the SBL.

Best regards,

XUE Fadong

0 Yogesh Siraswar 6 months ago in reply to Fadong XUE Fadong XUE

TI__Mastermind 20675 points

Could you please share DDR sysconfig tool version that you are using?

0 Fadong XUE Fadong XUE 6 months ago in reply to Yogesh Siraswar

Prodigy 160 points

Hello,Yogesh:

Best regards,

XUE Fadong

0 Yogesh Siraswar 6 months ago in reply to Fadong XUE Fadong XUE

TI__Mastermind 20675 points

Hi XUE,

We need to do some investigation and may take some time. But for your experiment purpose you may continue testing with 3730 MT/S.

Thanks

Yogesh

0 Biao Li 6 months ago in reply to Yogesh Siraswar

TI__Expert 6420 points

Hi Yogesh,

Any update?

BR,

Biao

0 Yogesh Siraswar 6 months ago in reply to Biao Li

TI__Mastermind 20675 points

Biao,

The key person supporting this from development team is out of office. Will try and get back early next week.

Thanks

Yogesh

0 Biao Li 6 months ago in reply to Yogesh Siraswar

TI__Expert 6420 points

Hi Yogesh,

Thanks for support, looking forward for your reply.

BR,

Biao

0 Yogesh Siraswar 6 months ago in reply to Biao Li

TI__Mastermind 20675 points

Biao,

This is known issue with SBL.( SITSW-1471)

Team is going to investigate this once the key expert returns.

Thanks

Yogesh

0 Yogesh Siraswar 5 months ago in reply to Yogesh Siraswar

TI__Mastermind 20675 points

Response from Development team:

According to DDR spec, we don't have to keep the PLL at exactly 933MHz, the customer can use 933.333333 KHz or 933.25 MHz.

The logic inside DM to calculate the multipliers to generate a particular frequency is very sensitive, because of which we don't want to touch it until there is a big blocker.

Just to give the depth of the problem, It will take at-least ~2 months of effort to update the driver.

0 Fadong XUE Fadong XUE 5 months ago in reply to Yogesh Siraswar

Prodigy 160 points

Hello,Yogesh:

Thanks for the support,

We have now obtained the AM62A7 (speed V), but still cannot set it to 933MHz,

We cannot generate 933.333333 MHz or 933.25 MHz through the sysconfig tool. May I ask if we can use 933.5 MHz?

Best regards,

XUE Fadong

0 Biao Li 5 months ago in reply to Fadong XUE Fadong XUE

TI__Expert 6420 points

Hi Fadong,

we suggest you setting to 1865 instead.

BR,

Biao

0 Fadong XUE Fadong XUE 5 months ago in reply to Biao Li

Prodigy 160 points

Hello,Li Biao,

OK. Thank you.

Best regards,

XUE Fadong

0 JJD 5 months ago in reply to Fadong XUE Fadong XUE

TI__Guru* 85990 points

Just to explain, i would recommend that you do not manually change the output file. The changes that you are suggesting could possibly violate timing since the tool calculated timing for 933MHz, but you would change to something higher (933.25 or 933.5)

I think the safest thing to do is just configure for 1865MHz as Biao said, this will allow the tool to configure everything for 1865MHz.

Regards,

James

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AM62A7: AM62A7(speed U) DDR overclock to 3733MT/s