AM623: Inquiry Regarding GPMC Timing

Hi Eiji,

First let me apologize for the long delay in this reply.

>>delay between two read accesses is significantly long
>>delay between two write accesses is only 3 clock cycles

>>1. Is the delay time between two read accesses reasonable?
Yes - it may differ slightly depending on the ARM core (A53 or M4)
>>2. Is it possible to reduce the delay?
Yes - see below
>>3. Will using DMA help in reducing the delay time between two read accesses?
Yes

When initiated by CPU or DMA, writes are queued (pipelined) from the VBUS interconnect allowing full utilization of the bandwidth of GPMC. Compiler optimization can control this write pipelining feature.
Reads however are issued one-by-one so the latency from CPU to GPMC module and back to CPU through the VBUS interconnect slows down consecutive accesses significantly.

Below assumes GPMC data bus width is 16-bit...
If the data type from CPU is increased to 32-bit then two GPMC read cycles travel together through the interconnect and can occur back-to-back from the GPMC pins without this latency between the 2 read accesses.

Using DMA avoids this latency so consecutive read accesses occur without the long delay between each access.

Another way increase read throughput is to use burst mode so one address is issued followed by upto 16 consecutive 16-bit read accesses. DMA is required to achieve a burst larger than 2 16-bit reads (a read to 32-bit data type from the CPU realizes a 2 16-bit read burst - address, 16-bit data, 16-bit data).

Hope this helps. Give it a try and let us know.