• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 721 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

McASP sync with AIC3106

ariel
Intellectual 335 points
Other Parts Discussed in Thread: TMS320C6748

Hi everyone,

I am using tms320c6748 for an audio project.

I want the AIC3106 to be on master mode and to produce the clock for the McASP.

In addition want to configure the input/output for an I2S sterio mode.

For some reason I receive noise at the output which means something In my McASP configuration is wrong.

Here are the main configuration which I beleive are related to the problem:

MCASP->RFMT = 0x0001807C-> this register configure the format of the input. The data is one bit delayed, (received one bit after the frame sync)

Msb first and slot size 16.data rotated (16 bits).

MCASP->RTDM = 0x00000003; activate slot 0 and slot 1

MCASP->AFSRCTL = 0x00000110; which means that the frame sync is externaly generated, one word width.

The configuration of the Tx registrs are similar to those of the Rx.

I suspect I don't fully understand the role of the frame sync in the I2S mode. Also I am not sure if I need to generate the frame sync externally or internally from the

RCLK (which itself is external). (as described in figure 17 p.27 on the manual)

In the AIC3106 I configured master mode (BCLK and WCLK for output) and I2S mode word length 32 bits. (registers 8 and 9 page 0)

Thanks in advance!

Ariel 

  • 0
    TI__Genius 14545 points

    Ariel,

       There is example code for this in the quickstartOMAPL1x_rCSL Package in the McASPEcho project for I2S streaming to AIC3106. You can use this as a reference to getting started with programming the McASP for I2S.

  • 0
    TI__Mastermind 29141 points

    ariel said:

    I suspect I don't fully understand the role of the frame sync in the I2S mode. Also I am not sure if I need to generate the frame sync externally or internally from the

    RCLK (which itself is external). (as described in figure 17 p.27 on the manual)

    Frame sync signal indicates the start a word and also indicates left or right channel.  Since you have the AIC3106 in master mode you want to have the McASP AFSX & ACLKX set as input.  The AFSR and ACLKR can be left unconnected.  AFSX should be connected to WCLK on the AIC and ACLKX to BCLK.  AHCLKX will not matter since the AIC will be generating the clock.

     

     

  • 0 in reply to Gus Martinez
    Intellectual 335 points

    Thanks Gus and Drew!

    I have seen in the examples that only in the Rx registers there is 1 bit delay. In the Tx registers there is not. that fixed my problem.

    Ariel