AM6422: MCU+ SDK: EPWM: EPWM_tbTimebaseClkCfg does not choose the optimal prescaler combination

Tool/software:

Description: The EPWM_tbTimebaseClkCfg function from epwm.c does not always calculate the optimal combination of hspClkDiv and lspClkDiv from the allowed values. This can result in suboptimal performance or incorrect configuration of the EPWM module. 

Expected Behavior: The function should select the optimal combination of hspClkDiv and lspClkDiv from the allowed values:

• hspClkDiv: 1, 2, 4, 6, 8, 10, 12, 14
• lspClkDiv: 1, 2, 4, 8, 16, 32, 64, 128

Actual Behavior: The function does not always select the optimal combination, leading to potential issues in the EPWM module configuration.

Example:

• moduleClk = 25,000,000 Hz
• tbClk = 25,000,000 / 128 = 195,312.5 Hz
• clkDiv = 128

Optimal Values:

• hspClkDiv = 1
• lspClkDiv = 128

Actual Values (according to current behavior):

• The function might incorrectly calculate hspClkDiv and lspClkDiv due to the current logic. For example, it could set:
  • hspClkDiv = 14 (maximum allowed value)
  • lspClkDiv = 8 (derived from 128 / 14)
• This results in an incorrect configuration since the divider results in 14*8=112, not 128. Thus, the actual tbClk is not moduleClk/128, as the user expects, but moduleClk/112
• All further user calculations and function calls using the tbClk will not be accurate, since the user expects the resulting frequency to be the one set after calling EPWM_tbTimebaseClkCfg

Actual clkDiv:

• clkDiv = 14 * 8 = 112 (which is not equal to the expected clkDiv of 128)

Proposal:

• Also provide a way to read back the resulting prescaler (HSPCLKDIV × CLKDIV) or at least the single prescaler values  

Environment:

• Hardware: AM6442
• SDK Version: AM64x MCU+ SDK v10.01.00.32
• Compiler: tiarmclang 4.0.1

Additional Information: The issue seems to arise from the logic used to determine the values of hspClkDiv and lspClkDiv. A more robust approach is needed to ensure the optimal combination is always selected.