TDA4VM: CPSW2G: FIFOs

Hi,

Hasan Aarzoo said:

Why the FIFO memory size is different in FIFO Memory Control (TRM: 12.2.1.4.6.5) and Receive FIFO Architecture (TRM: 12.2.1.4.6.10.5 )?

FIFO Memory Control (TRM: 12.2.1.4.6.5) is correct as per IP.
TRM: 12.2.1.4.6.10.5 would be with fifo block size of 4k.

Hasan Aarzoo said:

How the data flow occur across MAC port FIFO considering Tx (0-7) priority queues?

The packets will be forwarded to Priority Queues (0-7) as per PCP in packet as per default register mapping.
All non priority packets will forward to priority-0 queue.

Packet received to Host Port from internal cores to External port Queue, and similarly packet received on External port to Host Port Tx queue.

Best Regards,
Sudheer

Hi Sudheer,

Doredla Sudheer Kumar said:

TRM: 12.2.1.4.6.10.5 would wring from packet memory pint of view

Can you please explain more about the packet memory point of view?

Doredla Sudheer Kumar said:

All non priority packets will forward to priority-0 queue.

Why is it like that? Why not non-priority packets uses any other priority queue? Is it fixed from HW point of view?

Why there are no registers for Priority queue for Host port? Does Priority queues setting exits for Host Port?

Looking forward to hearing back from you.

Best Regards,
Hasan

Hi,

Hasan Aarzoo said:

Doredla Sudheer Kumar said:

TRM: 12.2.1.4.6.10.5 would wring from packet memory pint of view

Can you please explain more about the packet memory point of view?

It would be CPSW Architecture point of view with 4kb fifo block size 
But, CPSW IP is with 1kb fifo block size so, 20KB is total FIFO size per port for both Tx & Rx together.

Default 16KB allocated to Tx for all priorities 0 to 7 and 4KB to Rx.
You can allocate whole memory to single priority using TX_PRIx_MAXLEN_REG.

Hasan Aarzoo said:

Doredla Sudheer Kumar said:

All non priority packets will forward to priority-0 queue.

Why is it like that? Why not non-priority packets uses any other priority queue? Is it fixed from HW point of view?

If the incoming packet is VLAN packet then priority will be chosen from PCP.
If the packet is non-tagged and VLAN un-aware mode then priority is considered as Port-VLAN register priority by default it is 0 so, packet will be forwarded to Queue-0.

Hasan Aarzoo said:

Why there are no registers for Priority queue for Host port? Does Priority queues setting exits for Host Port?

Priority Queues exist for Host Port as well while receiving data from external ports based on priority packet will be forwarded to Host Port priority Queue.

Best Regards,
Sudheer

Hi Sudheer,

Doredla Sudheer Kumar said:

Priority Queues exist for Host Port as well while receiving data from external ports based on priority packet will be forwarded to Host Port priority Queue.

Is there any posibility to modify the size allocated for tx priority queues for Host Port?

Doredla Sudheer Kumar said:

20KB is total FIFO size per port

How can I allocate the the size of size of tx and rx for Host Port? For an instance 10 KB for Tx and 10 Kb for Rx for Host Port?

Also how can I allocate all 10 KB to tx priority queue 0 for Host Port?

Looking forward to hearing back from you.

Best Regards,
Hasan

Hi,

Hasan Aarzoo said:

Doredla Sudheer Kumar said:

Priority Queues exist for Host Port as well while receiving data from external ports based on priority packet will be forwarded to Host Port priority Queue.

Is there any posibility to modify the size allocated for tx priority queues for Host Port?

No. Host Port we can't change.
We can change only for external ports. Also, we can choose how much for Tx FIFO and Rx FIFO not for each priority Queue.
CPSW_PN_MAX_BLKS_REG is the one to choose how many blocks for Rx & how many for Tx.
By default 16 for Tx and 4 for Rx.

Hasan Aarzoo said:

How can I allocate the the size of size of tx and rx for Host Port? For an instance 10 KB for Tx and 10 Kb for Rx for Host Port?

Also how can I allocate all 10 KB to tx priority queue 0 for Host Port?

As informed we can't control Host Port buffer allocation.
FYI, No need to maintain more buffers at Host Port as Host Port can operate at much higher speed than external Port.

You can define required no.of buffers in Application software instead H/W buffers.

Best Regards,
Sudheer

Hi Sudheer,

Doredla Sudheer Kumar said:

Default 16KB allocated to Tx for all priorities 0 to 7 and 4KB to Rx.
You can allocate whole memory to single priority using TX_PRIx_MAXLEN_REG

Means I can allocate all 16KB to single priority?


Best Regards,
Hasan

Hi,

Hasan Aarzoo said:

Doredla Sudheer Kumar said:

Default 16KB allocated to Tx for all priorities 0 to 7 and 4KB to Rx.
You can allocate whole memory to single priority using TX_PRIx_MAXLEN_REG

Means I can allocate all 16KB to single priority?

It won't be possible to have whole 16KB to single priority, we haven't tested this.
Basically above register will limit the Max frame size with priority on CPSW, But CPSW can support maximum of 2024 frame size beyond can't be supported.
So, you have to configure above register of each priority with maximum of 2024, not beyond that.

As suggested above, you can manage S/W buffers in application and have the default memory of CPSW ports as is.

Best Regards,
Sudheer

Hi Sudheer,

Doredla Sudheer Kumar said:

As informed we can't control Host Port buffer allocation.
FYI, No need to maintain more buffers at Host Port as Host Port can operate at much higher speed than external Port.

In that case, how much memory is allocated for Tx and Rx buffers for Host Port?

Doredla Sudheer Kumar said:

If the packet is non-tagged and VLAN un-aware mode then priority is considered as Port-VLAN register priority by default it is 0 so, packet will be forwarded to Queue-0.

I am transmitting packets which are non-tagged and VLAN un-aware mode. Since all the packets will be transmitted from Tx priority queue 0 and we have a max. limit of 2024 bytes for TX_PRIx_MAXLEN_REG.

Questions:

1. Is it advisable to allocate 2 KB for Tx buffer (all for TX_PRI0_MAXLEN_REG other queues set to 0) and 18 KB for Rx buffer?
   
   
2. How the ethernet packets are transferred to allocated memory from Rx buffer of MAC Port through switch fabric and then to Host port?
   For an instance, I have 9 KB (space for 6 ethernet frame of 1.5 KB each) of memory allocated in OCRAM for the etherent packets received from CANoe. As Rx buffer of MAC Port is 18 KB  and I sent a 12 ethernet frames of 1.5 KB each from CANoe. All the frames are received in the Rx buffer of MAC port, 6 packets are received in the OCRAM, what will happen to the rest 6 packets?
   
   Will they remain in Rx buffer of MAC Port and transferred to OCRAM when I retrieve rx frames using dma and qeueues the old 6 packets?
   
   Is it the way how Rx buffer for MAC Port works or am i missing some details?
   
   
   

Best Regards,
Hasan

Hi,

Hasan Aarzoo said:

Doredla Sudheer Kumar said:

As informed we can't control Host Port buffer allocation.
FYI, No need to maintain more buffers at Host Port as Host Port can operate at much higher speed than external Port.

In that case, how much memory is allocated for Tx and Rx buffers for Host Port?

As informed earlier by default allocation of 20KB is 16KB for Tx and 4KB for Rx.

Hasan Aarzoo said:

Is it advisable to allocate 2 KB for Tx buffer (all for TX_PRI0_MAXLEN_REG other queues set to 0) and 18 KB for Rx buffer?

There is no such allocation available for Host Port, it is fixed allocation 16KB for Tx and 4KB for Rx.
Above will drop the packet when size is more than value specified in MAXLEN_REG. It won't decide the FIFO size.

Hasan Aarzoo said:

How the ethernet packets are transferred to allocated memory from Rx buffer of MAC Port through switch fabric and then to Host port?
For an instance, I have 9 KB (space for 6 ethernet frame of 1.5 KB each) of memory allocated in OCRAM for the etherent packets received from CANoe. As Rx buffer of MAC Port is 18 KB  and I sent a 12 ethernet frames of 1.5 KB each from CANoe. All the frames are received in the Rx buffer of MAC port, 6 packets are received in the OCRAM, what will happen to the rest 6 packets?

Will they remain in Rx buffer of MAC Port and transferred to OCRAM when I retrieve rx frames using dma and qeueues the old 6 packets?

Is it the way how Rx buffer for MAC Port works or am i missing some details?

Yes, your underrating is correct. The data flow works as you mentioned above but size of FIFO are different as I have mentioned above.

Best Regards,
Sudheer

Hi Sudheer,

This question was in respect to MAC Port FIFO.

Hasan Aarzoo said:

Doredla Sudheer Kumar said:

If the packet is non-tagged and VLAN un-aware mode then priority is considered as Port-VLAN register priority by default it is 0 so, packet will be forwarded to Queue-0.

I am transmitting packets which are non-tagged and VLAN un-aware mode. Since all the packets will be transmitted from Tx priority queue 0 and we have a max. limit of 2024 bytes for TX_PRIx_MAXLEN_REG.

Questions:

1. Is it advisable to allocate 2 KB for Tx buffer (all for TX_PRI0_MAXLEN_REG other queues set to 0) and 18 KB for Rx buffer?

1. Is it advisable to allocate 2 KB for Tx buffer (all for TX_PRI0_MAXLEN_REG other queues set to 0) and 18 KB for Rx buffer?
   or should I use the default settings for MAC Port FIFO (16 KB Tx buffer and 4 KB Rx Buffer)?

Best Regards,
Hasan

Hi,

Hasan Aarzoo said:

1. Is it advisable to allocate 2 KB for Tx buffer (all for TX_PRI0_MAXLEN_REG other queues set to 0) and 18 KB for Rx buffer?

1. Is it advisable to allocate 2 KB for Tx buffer (all for TX_PRI0_MAXLEN_REG other queues set to 0) and 18 KB for Rx buffer?
   or should I use the default settings for MAC Port FIFO (16 KB Tx buffer and 4 KB Rx Buffer)?

You can change the no.of blocks allocation to Tx & Rx for MAC Port using CPSW_PN_MAX_BLKS_REG register.

Best Regards,
Sudheer

Hi Sudheer,

I want to clarify another doubt about Tx buffer in Mac port. I have set TX_PRI0_MAXLEN_REG to 2024. I am only transmitting non-vlan tagged packets and cpsw in in vlan unaware mode. So all transmission though TX_PRI0_MAXLEN_REG.

1. Consider a case where I have 2 KB allocated for MAC Port Tx buffer. I am continuously enqueuing 1.5 KB ethernet packets to UDMA for transmission. How will the transmission happen across MAC port Tx Buffer?
   
   For instance, will the Tx priority queue 0 will transmit ethernet packets one by one, 1.5 KB transmission first rest 0.5 KB remain unsed and same for other packets.
   
   will the Tx priority queue 0 will transmit ethernet packets like 1.5 KB transmission first rest 0.5 KB is filled with data of packet 2 and with the 2nd go of priority queue, 1KB is used for remaining data of 2nd ethernet packet and so on
   
   
   
2. What is the use case to have Tx buffer for MAC Port when TX_PRI0_MAXLEN_REG can use only 2024 bytes maximum?
   
   

Best Regards,
Hasan

Hi,

Hasan Aarzoo said:

What is the use case to have Tx buffer for MAC Port when TX_PRI0_MAXLEN_REG can use only 2024 bytes maximum?

It is for limiting the packet size not beyond the number specified but, Tx buffer can be more than that can accommodate more packets at H/W FIFO.

Hasan Aarzoo said:

Consider a case where I have 2 KB allocated for MAC Port Tx buffer. I am continuously enqueuing 1.5 KB ethernet packets to UDMA for transmission. How will the transmission happen across MAC port Tx Buffer?

For instance, will the Tx priority queue 0 will transmit ethernet packets one by one, 1.5 KB transmission first rest 0.5 KB remain unsed and same for other packets.

As per knowledge, Internal H/W will work in above fashion i.e. if whole data can accommodate in FIFO then only transfer will be initiated.

Best Regards,
Sudheer

Hi Sudheer,

Doredla Sudheer Kumar said:

Doredla Sudheer Kumar said:

As informed we can't control Host Port buffer allocation.
FYI, No need to maintain more buffers at Host Port as Host Port can operate at much higher speed than external Port.

In that case, how much memory is allocated for Tx and Rx buffers for Host Port?

As informed earlier by default allocation of 20KB is 16KB for Tx and 4KB for Rx.

As discussed previously, there is fixed size FIFO for Host port in CPSW2G. But the TRM says in the register definition above that there is no Tx FIFO for HOST Port?

Best regards,
Hasan

Hi, 

Hasan Aarzoo said:

As discussed previously, there is fixed size FIFO for Host port in CPSW2G. But the TRM says in the register definition above that there is no Tx FIFO for HOST Port?

Above info might be wrong, let me confirm the same with our IP owner. 

Best Regards, 

Sudheer

Hi Sudheer,

Looking forward to hearing back from you.

Best Regards,
Hasan

Hi,

I have requested our IP team to confirm the above, once i have received an update from them will share with you.

Best Regards,
Sudheer

Hi,

As per information from IP team, It has few blocks of memory for  handing of packets sent from External Port to Host Port.
It is not as same as External Port Tx FIFO i.e. 16KB in case of CPSW2G, for CPSW5G/CPSW9G is has 16KB as in case of CPSW2G only single external port ingress can go to Host Port so, it is termed as no TXFIFO in TRM.

Best Regards,
Sudheer

Hi Sudheer,

Doredla Sudheer Kumar said:

As per information from IP team, It has few blocks of memory for  handing of packets sent from External Port to Host Port.

Can you please tell me how much is this few block of memory? For an instance, 4 KB or 8 KB?

How much memory is then allocated for Rx Host Port FIFO?

Best regards,
Hasan 

Hi Sudheer,

Based on the entire discussion which we had in this ticket, I am sharing a picture according to my understading about CPSW2G FIFO's.
Can you please confirm whether my understand is correct or not? If not, can you please suggest changes in the proposed diagram?

Best regards,
Hasan