AM6412: power up timing delays

Hello Bruno

Thank you for the query.

VMON_VSYS

This is a fail-safe input and connected through a divider. You could connect Main or SYS voltage to monitor.

The supply could be used for early detection of the board supply failure.

Connecting the supply that is used to generated the on-board supplies through a resistor divide is recommended/

Refer SOC data sheet : System Power Supply Monitor Design Guidelines

VMON_3P3_MCU Voltage monitor for 3.3 V MCU power supply 3.135 3.3 3.465 V
VMON_3P3_SOC Voltage monitor for 3.3 V SoC power supply 3.135 3.3 3.465 V

These are SOC supply monitors and need to connect to any the SOC sys voltage that connects to the SOC IO supply for IO group VDDSHVx

Bruno B said:

By the way the datasheet figiure 7-5 does not give any range for the timing delays during power up sequence.

What are the minimum delays ? what are the maximum delays ?

There is no Min or Max delay.

it is recommended to ramp the next supply after the current supply ramps and becomes stable.

Regards,

Sreenivasa

Hello Kallikupa,

Thank you for your reply.

1 - One thing clear : The VMON VSYS is connected to 3V3 primary source by Resistor divider. No problem with this

2 - On our board all the VDDSHVxx will be 1V8 : We don't use at all 3V3 interfaces for this application (VDDA_3P3_SDIO, VDDA_3P3_USB0 will be connected to GND because unused) .

Therefore my question remains : Is it possible to connect both VMON_3P3_MCu and VMON_3P3_SOC to the 3V3 primary voltage ?. 

The only consequence I can see is that the powerup sequence will look like the figure 7-5 but with first "rail" VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,VDDSHV4 , VMON_3P3_SOC , VMON_3P3_MCU) rising at the same moment as VMON_VSYS input (time delay = 0 in that case)

3 - From figure 7-5 I understand that (VDDS_DDR , VDDS_DDR_C) can be established before , or after VDD_CORE. 

do you confirm ?

4 - On thing that remains unclear is the number of clock cycles that must happen before MCU_PORz is asserted. 

Can this be precised ?

With best regards,

Bruno

Hello Bruno,

Regarding VDD_CORE and VDDR_COTE

Bruno B said:

3 - From figure 7-5 I understand that (VDDS_DDR , VDDS_DDR_C) can be established before , or after VDD_CORE. 

do you confirm ?

Please read the notes after the sequence diagram

I copied the relevant note:

10. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +10. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down afterVDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirementsbeyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered bythe same source so they ramp together when VDD_CORE is operating at 0.85V.

 Regards,

Sreenivasa

Hello Bruno,

Bruno B said:

4 - On thing that remains unclear is the number of clock cycles that must happen before MCU_PORz is asserted. 

Can this be precised ?

We have this specified in terms of ms time delay. 

Please refer below.

Table 7-5. MCU_PORz Timing Requirements
see Figure 7-7
NO. PARAMETER MIN MAX UNIT
RST1
th(SUPPLIES_VALID - MCU_PORz)
Hold time, MCU_PORz active (low) at Power-up
after supplies valid (using external crystal circuit) 9500000 ns

Thanks,

Sreenivasa

Hello Kallikupa,

Thanks again for your last replies.

Still remains the question 2 about VMON_VSYS.

regards

Bruno

Hello Bruno,

Bruno B said:

- On our board all the VDDSHVxx will be 1V8 : We don't use at all 3V3 interfaces for this application (VDDA_3P3_SDIO, VDDA_3P3_USB0 will be connected to GND because unused) .

Therefore my question remains : Is it possible to connect both VMON_3P3_MCu and VMON_3P3_SOC to the 3V3 primary voltage ?. 

This is not recommended due to the fail-safe concern.

Grounding VMON_3P3 MCU and SOC inputs is an option.

I am confirming with our device expert and will update when i hear from him.

Regards,

Sreenivasa

Sorry Kallikupa,

May I come back again to my question 3 :

You are pointing out some contraints about VDD_CORE and VDDR_CORE, But my question was about VDDS_DDR (VDDS_DDR_C) relative to VDD_CORE.

regards,

Bruno

Hello Bruno,

Thank you for the note.

Bruno B said:

You are pointing out some contraints about VDD_CORE and VDDR_CORE, But my question was about VDDS_DDR (VDDS_DDR_C) relative to VDD_CORE.

Understand.

Bruno B said:

3 - From figure 7-5 I understand that (VDDS_DDR , VDDS_DDR_C) can be established before , or after VDD_CORE. 

do you confirm ?

This is correct.

Regards,

Sreenivasa

HI Kallikupa,

I have another question still relative to figure 7-5

We can see that MCU_OSC0_XI Clock input must be '0" untill all power supplies are stable, and then become active

However when looking at the EVM schematics (TMDS64EVM/ PROC101C(004)) and then making some physical measurement I can see that this condition is not respected

the picture shows

: upper screen: P0V85 VDDR_CORE mixed with MCU clock input ==> MCU happens to be active about 1.5 ms before P0V85

: lower screen : MCU_clock ZOOM at the moment where clock begins to be active ==> clock measurement : 25 MHz : OK

Is this legal ?

is this tolerated ?

With best regards

Bruno

Hello Bruno,

Thank you for the inputs.

Please refer below FAQ

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1433049/faq-am625-am623-am625sip-am625-q1-am620-q1-custom-board-hardware-design-queries-regarding-mcu_osc0-start-up-time

Bruno B said:

the picture shows

: upper screen: P0V85 VDDR_CORE mixed with MCU clock input ==> MCU happens to be active about 1.5 ms before P0V85

: lower screen : MCU_clock ZOOM at the moment where clock begins to be active ==> clock measurement : 25 MHz : OK

Is this legal ?

is this tolerated ?

This is not a concern. The timing diagram in the data sheet covers the worst case.

Regards,

Sreenivasa

Thank you Kallikupa,

The FAQ you are refering to does not really match the EVM case since in the EVM the clock comes from an external source, not from a crystal dependent upon VDDS_OSC.

In the EVM the clock starts toggling a long before all power supplies are applied to the MCU.

About your assertion : "This is not a concern. The timing diagram in the data sheet covers the worst case. : Should I understand that the few toggling shown in fig 7-5 are the minimum ones (actually 1,2µs required) , and that they could have started before, independently of power supplies ?

You confirm ?

Regards,

Bruno

Hello Bruno,

Thank you.

Table 6-5. MCU_PORz Timing Requirements

Are you referring to this table for the 1.2 uS time.

This is the min time the clock needs to be available after the supply ramps before the MCU_PORz goes high (SOC released from reset).

Regards,

Sreenivasa

Yes, table 7-5 actually

Hello Bruno,

Thank you.

Please ensure you use the lates data sheet on TI.com, in case you have a older version.

Regards,

Sreenivasa

OK thanks for the advice !,

I downloaded the latest version

But do you confirm :

About your assertion : "This is not a concern. The timing diagram in the data sheet covers the worst case. : Should I understand that the few toggling shown in fig 6-5 are the minimum ones (actually 1,2µs required) , and that they could have started before, independently of power supplies ?

Regards,

Bruno

Hello Bruno,

Thank you.

Bruno B said:

But do you confirm :

About your assertion : "This is not a concern. The timing diagram in the data sheet covers the worst case. : Should I understand that the few toggling shown in fig 6-5 are the minimum ones (actually 1,2µs required) , and that they could have started before, independently of power supplies ?

The clock needs to be stable before the MCU_PORz is released

The MCU_PORz can be released only after the supplies ramp and the oscillator is stable.

The above understanding is correct.

Regards,

Sreenivasa