AM6442: TRM question - section 12.1.5 - can any UART in the IC run full duplex (including MCU_UARTn)

Hello Jim Mrowca,

Thank you for the query.

I do not expect any issues with the hardware but i am not sure if there are any software concerns.

Let me check with the team internally and update you.

Could you share the development environment/Platform you would or using.

Regards,

Sreenivasa

Sreenivasa:

 Three specific "domain" followups per your RFI

1. Can I use the MCU_UART up to 3.6Mbps data rate as full duplex with an RS-485 full duplex transceiver?
2. Can I run an "SoC" UART (ether A53 or R5 core controlled) up to 12Mbps data rate, given I use either a 160MHz or 192MHz functional clock, as full duplex with an RS-485 full-duplex transceiver?
3. Up to what Mbps data rate, using 8 bit data, can one run a PRU_ICSSG UART, as full duplex with an RS-485 full-duplex transceiver?

thanks

Jim

I am on the TMDS64EVM with the AM64x SDK v10.1

Hello Jim Mrowca,

Thank you.

Are you checking if the implementation is feasible or if we have tested these interfaces on the EVM for these speeds?

Would you please share the requirements you have?

Regards,

Sreenivasa

Hi,

I am assuming this is your use case, please correct me if I am wrong.

Use Case:

Suppose UART0 is in use and the customer wants to send some data from the UART0 via UART0_TX externally and receive some data on the UART0_RX from sender simultaneously using two threads.

My Comments if the use case is correct:

Our SDK examples are not tested on the Full Duplex capability. Is it possible for the customer to test it out? If yes, then I would suggest them creating 2 threads, first thread writes and the second threads reads. The UART instance should be the same, for example UART0. If the customer is not having bandwidth do let me know.

Internally in UART_write and UART_read APIs we use semaphores, but these are separate so yes full duplex is possible, but this needs to be tested as mentioned in the previous response.

Regards,

Vaibhav

Vaibhav & Sreenvisa:

How difficult is it to take the AM64x SDK v10.1 " uart_echo_dma_lld.c " and split the TX & Rx processes into 2 tasks that the main.c of the "UART Echo DMA LLD" example?

With the data rates that are capable in the SoC UARTs, I feel that going full duplex would be a well desired feature effectively nearly doubling the throughput vs restricting one to a half duplex configuration!

Given what I read in the TRM section 12.1.5.4 and the Figure 12-259 block diagram, you are seriously limiting the hardware capability for the AM64x on serial ports.

regards

Jim

cc:

m-bhatnagar@ti.com m-firth@ti.com 

Hello Jim, 

Thank you for the inputs.

Let me review the inputs and comeback.

Regards,

Sreenivasa