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Turn Around Time

1258021
Genius 5120 points

Other Parts Discussed in Thread: OMAP-L138

Hi,

We are using 16C754C UART Controller from TI. It is interfaced using EMIFA bus.

EMIFA Clk frequency is 100MHz.

there is a Write and Read delay requirement of 85nS two successive reads and writes.

How can we provide 85nS delay using EMIFA?

I was referring OMAP-L138 TRM  Literature Number: SPRUH77A October 2011.

In this document for Figure 20-10, Turn around time was not shown in this document.

Can someone please explain me how should I interpret signals during Turn Around Time.

Regards,

GSR

  • 0
    TI__Genius 17116 points

    GSR,

    You are correct that there are no figures in the TRM showing the Turnaround period.  However, please take a look at the tables in sections 20.2.5.4.1/2 and 20.2.5.5.1/2 for a text description.  The CS, OE, and WE will all be inactive high during the turn around period.  Also, the address bus will be invalid and the data bus will not be driven.

    -Brad

  • 0 in reply to B.C.
    Genius 5120 points

    Hi Brad,

    Thank You for the information.

    Is there a way to achieve 90nS Turn Around Time when EMIF is operating at 100MHz?

    Regards,

    GSR

  • 0 in reply to 1258021
    TI__Genius 17116 points

    GSR,

    The max value that you can program in the TA field is 0x3, which translates into 4 clock cycles.  At 100MHz, this results in a turn around time of 40ns.  If 90ns is required, you can increase the hold period to 50ns to reach a total 90ns between WE/OE deactivating and the start of the next SETUP period.  See the following quote from the TRM:

    "If more turnaround cycles are required than can be programmed into the TA field, additional cycles can be added to the R_HOLD field to compensate."

    Regards,

    Brad

  • 0 in reply to B.C.
    Genius 5120 points

    Hi Brad,

    Thank You for the reply and your time.

    The turn around value 90nS is required between either two reads or writes and a read and write.

    So, if we add it to R_HOLD, will this be accounted for Write operation also? or do we have to write into W_HOLD?

    Regards,

    GSR

     

  • 0 in reply to 1258021
    TI__Genius 17116 points

    GSR,

    Yes, you should also add extra cycles to W_HOLD if you need to ensure a minimum delay following a write operation.

    Regards,

    Brad

  • 0 in reply to B.C.
    Genius 5120 points

    Hi Brad,

    Thank You for the reply and your time.

    Regards,

    GSR