TDA4VM-Q1: try read and write SRAM of 8MB(MSMC) with ECC 3*512KB SRAM,

jayadeva sm

Prodigy 50 points

Part Number: TDA4VM-Q1

Tool/software:

Hello Team,

I am try read and write SRAM of 8MB(MSMC) with ECC 3*512KB SRAM,

not enable to find address of memory address start and end

Please help on this,

Thank you

Jayadeva

7 months ago

0 Kevin S 7 months ago

TI__Mastermind 38510 points

Hi,

I am not sure I fully understand your question.

MSMC SRAM starts at address 0x7000 0000 and would end at 0x707F FFFF for a system with 8MB MSMC SRAM.

Regards,
Kevin

0 jayadeva sm 7 months ago in reply to Kevin S

Prodigy 50 points

Hi,

i am checking complete SRAM can access write and read, to do that i need address

i check for above address 0x7000 0000 it can read,

but i try to 0x707F0000 its crushed in EVB board below logs, SW is SDK10,

please support on this how can check SRAM of 8MB(MSMC) with ECC 3*512KB SRAM,

root@j784s4-evm:~# devmem2 0x70000000
/dev/mem opened.
Memory mapped at address 0xffff8194d000.
Read at address 0x70000000 (0xffff8194d000): 0xAA0003F4
root@j784s4-evm:~# devmem2 0x707F0000
/dev/mem opened.
[ 63.351937] SError Interrupt on CPU6, code 0x00000000bf000000 -- SError
[ 63.351949] CPU: 6 PID: 1222 Comm: devmem2 Tainted: G O 6.6.32-ti-gdb8871293143-dirty #1
[ 63.351954] Hardware name: Texas Instruments J784S4 EVM (DT)
[ 63.351956] pstate: 60000000 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 63.351960] pc : 0000ffff95044450
[ 63.351962] lr : 0000ffff950466a0
[ 63.351963] sp : 0000ffffe5591550
[ 63.351964] x29: 0000ffffe5591550 x28: 0000ffffe5591720 x27: 0000000000000000
[ 63.351970] x26: 0000000000420000 x25: 0000ffff95070000 x24: 0000ffffe5591918
[ 63.351975] x23: 0000000000000003 x22: 0000000000000002 x21: 0000ffff95077350
[ 63.351979] x20: 0000000000001000 x19: 0000ffff95070000 x18: 0000000000000003
[ 63.351983] x17: 0000ffff95046658 x16: 000000000041fff8 x15: 0000ffff95064cd0
[ 63.351988] x14: 0000000000000001 x13: 0000ffffe5591670 x12: 00000000ffffffc8
[ 63.351992] x11: 00000000ffffff80 x10: 000000000000000a x9 : 0000000000000000
[ 63.351996] x8 : 0000000000000040 x7 : 3030303037303539 x6 : 0000000000400358
[ 63.352000] x5 : 0000000000000000 x4 : 0000ffffe5591549 x3 : 0000000000000000
[ 63.352004] x2 : 000000000041fe78 x1 : 0000000000000048 x0 : 0000000000000000
[ 63.352010] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 63.352012] CPU: 6 PID: 1222 Comm: devmem2 Tainted: G O 6.6.32-ti-gdb8871293143-dirty #1
[ 63.352016] Hardware name: Texas Instruments J784S4 EVM (DT)
[ 63.352018] Call trace:
[ 63.352020] dump_backtrace+0x90/0xe8
[ 63.352036] show_stack+0x18/0x24
[ 63.352041] dump_stack_lvl+0x48/0x60
[ 63.352045] dump_stack+0x18/0x24
[ 63.352048] panic+0x324/0x380
[ 63.352053] nmi_panic+0x8c/0x90
[ 63.352057] arm64_serror_panic+0x6c/0x78
[ 63.352062] do_serror+0x3c/0x70
[ 63.352066] __el0_error_handler_common+0x40/0xa4
[ 63.352071] el0t_64_error_handler+0x10/0x1c
[ 63.352074] el0t_64_error+0x190/0x194
[ 63.352077] SMP: stopping secondary CPUs
[ 63.352092] Kernel Offset: disabled
[ 63.352093] CPU features: 0x0,80000200,28020000,1000420b
[ 63.352096] Memory Limit: none
[ 63.542690] ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---

thank you

Jayadeva SM

0 Kevin S 7 months ago in reply to jayadeva sm

TI__Mastermind 38510 points

Hi,

The MSMC SRAM can be used as cache memory. The memory space occupied by the cache is no longer accessible as memory-mapped SRAM. Thus while the MSMC has 8MB of SRAM, this amount will be effectively reduced when the SRAM is also used as cache memory.

Can you check how the MSMC_CACHE_CTRL register is configured in your system?

Regards,
Kevin

0 jayadeva sm 7 months ago in reply to Kevin S

Prodigy 50 points

Hello Kevin,

please have meeting to discuss about this on Monday your available time i schedule meeting,

how to check Configuration register?

i have some more discussion on SRAM of 8MB(MSMC) with ECC 3*512KB SRAM,

Thank you

Jayadeva

0 Jeyaseelan Kirubaharan 7 months ago in reply to jayadeva sm

Intellectual 755 points

Hi Kevin,

We are planning to use some "unused" internal memory for a test application from A72 core. Any region in this 8MB internal memory shall be usable from A72 core. If so ,what is the start of this internal memory address and the length to which it could be usable for the same.

With regards,

Jeyaseelan

0 Kevin S 7 months ago in reply to jayadeva sm

TI__Mastermind 38510 points

jayadeva sm said:
how to check Configuration register?

You can read the value at 0x6E001000.

Jeyaseelan Kirubaharan said:
We are planning to use some "unused" internal memory for a test application from A72 core. Any region in this 8MB internal memory shall be usable from A72 core. If so ,what is the start of this internal memory address and the length to which it could be usable for the same.

I am sorry but I don't understand what you are asking, and I do not know anything about your system and how you have allocated memory.

As I indicated previously, MSMC SRAM starts at address 0x7000 0000 and would end at 0x707F FFFF for a system with 8MB MSMC SRAM.

If you are using part or all of the MSMC SRAM as cache, then the available memory space to be used as SRAM would reduce.

Regards,
Kevin

0 Jeyaseelan Kirubaharan 7 months ago in reply to Kevin S

Intellectual 755 points

Hi Kevin,

We are using the Linux J784S4 SDK from TI . And the kernel runs from external memory (LPDDR) through A72 Core. No other cores are used. So the Cache initialization would have been handled from SDK linux only. Please if possible if you have the usage details kindly let us know. We are looking for some unused areas from internal memory other than Caches or peripheral registers etc.

With regards,

Jeyaseelan

0 Kevin S 7 months ago in reply to Jeyaseelan Kirubaharan

TI__Mastermind 38510 points

I'll re-assign the ticket to our software team. However, you can read the MSMC_CACHE_CTRL register to see if it is set to a non-zero value.

Regards,
Kevin

0 Keerthy J 7 months ago in reply to Kevin S

TI__Guru**** 163290 points

Hi,

Are you using the default SDK of J784s4. Can you confirm which SDK version?

Also Subject quotes:

TDA4VM-Q1

Can you please confirm the SOC and exact SDK version in use here?

Also look at Linux SDK source file:

arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi

        msmc_ram: sram@70000000 {
                compatible = "mmio-sram";
                reg = <0x00 0x70000000 0x00 0x800000>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0x00 0x00 0x70000000 0x800000>;

                atf-sram@0 {
                        reg = <0x00 0x20000>;
                };

                tifs-sram@1f0000 {
                        reg = <0x1f0000 0x10000>;
                };

                l3cache-sram@200000 {
                        reg = <0x200000 0x200000>;
                };
        };

There are reserved memory regions that we cannot use.

Try to use 0x70400000 + Size that you need. Check if that works.

- Keerthy

0 Jeyaseelan Kirubaharan 7 months ago in reply to Keerthy J

Intellectual 755 points

Hi Keerhy,

It was mistakenly quoted . SoC is TD4VH and SDK version is 10.0.1. Right now we can able to do Read/Write some memory from address 0x70400000. This could serve or purpose now. Thanks for your support.

With regards,

Jeyaseelan

Processors

Processors forum

TDA4VM-Q1: try read and write SRAM of 8MB(MSMC) with ECC 3*512KB SRAM,

TDA4VM-Q1