Hi
I have written a UPP driver on our DSP (OMAP-L138) and at first I thought everything was well.
We have a FPGA connected to the OMAP-L138 which uses 2 UPP channels (I & Q). The DSP is the receiver on both channels (FPGA is sending data to DSP on both channels).
If both channels initiates a transfer eg. at a 10KHz rate everything seems OK, the data received is valid (this also seems to be ok if one channel initiates transfers at 5KHz and the other at 10KHz). But if one of the channels runs async. of the other (like one at 10KHz and the other a little bit slower) I get some problems with my HWI ISR routine. The HWI ISR follows UPP pseudocode guidelines:
1. interrupts = UPIER
2. While (interrupts)
{
process and clear each interrupt
interrupts = UPIER
}
3. UPEOI = 0
If I protect my HWI ISR with HWI_disable() and HWI_restore() everything seems fine. So it seems that sometimes my UPP HWI ISR gets interrupted more than once eventhough the UPEOI has not been cleared?
Is this possile - or is this one of the bugs in the chip described in the errata (A Single CHIPINTn Interrupt Event Will Register Multiple Times in the DSP Event Combiner Module (ECM) )
Hope someone can help me?
Many thanks,
Mads
