J721EXCPXEVM: errata i2310 (USART: Erroneous clear/trigger of timeout interrupt) applies if interruptsaren't used

Marcel Bals

Part Number: J721EXCPXEVM
Other Parts Discussed in Thread: DRA829, TDA4VM

Tool/software:

In Errata analysis

J721E DRA829/TDA4VM Processors Silicon Revision 2.0/1.1/1.0 (Rev. E)
https://www.ti.com/lit/pdf/sprz455?keyMatch=j721e&tisearch=universal_search&f-technicalDocuments=Errata

Does errata i2310 (USART: Erroneous clear/trigger of timeout interrupt) applies if interrupts are disabled?

9 months ago

0 Chris Tsongas 9 months ago

TI__Genius 16140 points

Your question has been initially assigned to Neehar

+1 Andreas Dannenberg 9 months ago in reply to Chris Tsongas

TI__Guru 70172 points

Marcel,

I'm not the assigned engineer for this product family but I was just working on something very much related and came across your post here and wanted to share my findings:

Marcel Bals said:
Does errata i2310 (USART: Erroneous clear/trigger of timeout interrupt) applies if interrupts are disabled?

According to this post here, interrupts need to be enabled: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1393731/tda4vm-uart-i2310-errata/5344611#5344611

Further, I found in the TRM that the timeout mechanism is tied to the receive interrupt, see here:

Hope that clarifies things.

Regards, Andreas

0 Marcel Bals 9 months ago in reply to Andreas Dannenberg

Prodigy 10 points

Hi ANdreas,

many thanks .

I stumpled also over the same thread yesterday.

Regards

Marcel

0 Neehar Sawant 9 months ago in reply to Marcel Bals

TI__Mastermind 21860 points

Hi Marcel,

Thank you Andreas for providing a response in my absence.

Sorry for the delay Marcel. Andreas is correct, this errata will only concern you if you have interrupts enabled. With interrupts disabled, you will not have to worry about timeout at all.

Thanks,

Neehar

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J721EXCPXEVM: errata i2310 (USART: Erroneous clear/trigger of timeout interrupt) applies if interruptsaren't used