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PROCESSOR-SDK-J784S4: DSI 0 output - HSync error

Part Number: PROCESSOR-SDK-J784S4
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hello TI,

We are working with the TDA4VH on our custom board and are trying to enable DSI0 output. (We are using Processor_SDK_j784s4 version 10)

DSI0 output is connected to the GMSL2 serializer/deserializer further.

We do have situation that PCLK is detected and VS is detected, but HS is not detected.

Both TDA4 and serializer show same error indications.

  • We are using single-cam-app as test app (camera is working and is sending 30FPS).
  • Display settings that we set in the code are:
  • 4 lanes, 391.58Mbps lane speed, refClock 20Mhz., FPS 60
Htot 1420
Hactive 1280
Hfp 100
Hsw 20
Hbp 20
Vtot 766
Vactive 720
Vfp 32
Vsw 4
Vbp 10

Params are changed on more then one place, according to the other threads on the forum.

When we check the registers with devmem2, during running use case, we get following:

root@j784s4-evm:~# devmem2 0x048000EC
/dev/mem opened.
Memory mapped at address 0xffff95ce9000.
Read at address  0x048000EC (0xffff95ce90ec): 0x00000023
root@j784s4-evm:~# devmem2 0x048000C0
/dev/mem opened.
Memory mapped at address 0xffffa7adf000.
Read at address  0x048000C0 (0xffffa7adf0c0): 0x0030002E
root@j784s4-evm:~# devmem2 0x048000B4
/dev/mem opened.
Memory mapped at address 0xffff99586000.
Read at address  0x048000B4 (0xffff995860b4): 0x00020284
root@j784s4-evm:~# devmem2 0x048000C4
/dev/mem opened.
Memory mapped at address 0xffff8e46e000.
Read at address  0x048000C4 (0xffff8e46e0c4): 0x01260F00
root@j784s4-evm:~# devmem2 0x048000F0
/dev/mem opened.
Memory mapped at address 0xffffb6211000.
Read at address  0x048000F0 (0xffffb62110f0): 0x00000004
root@j784s4-evm:~#

In the dss_dctrlDsi.c file we noticed following code block (function dssDctrlUpdateVideoSizeConfig)

We have set vFrontPorch to our forwarded value, and VSync is detected.

But for the hSync apart from multiplication with BPP, additional values are used: 14,12,6,20.

Can you explain these values, and how are they calculated?

        horzTotal = mInfo->width + mInfo->hFrontPorch + mInfo->hBackPorch + mInfo->hSyncLen;

        dsiObj->videoSizeCfg.vact = mInfo->height;
        if (DSS_DSI_CONNECTION_DSI2DP_BRIDGE != connectedTo)
        {
            dsiObj->videoSizeCfg.vfp = 1;
        }
        else
        {
            //We have forced entering here, even we do not have DSI2DP bridge
            dsiObj->videoSizeCfg.vfp = mInfo->vFrontPorch;
        }

        dsiObj->videoSizeCfg.vbp = mInfo->vBackPorch;
        dsiObj->videoSizeCfg.vsa = mInfo->vSyncLen;
        dsiObj->videoSizeCfg.hsa = (mInfo->hSyncLen * BPP) - 14U;
        dsiObj->videoSizeCfg.hbp = (mInfo->hBackPorch * BPP) - 12U;
        dsiObj->videoSizeCfg.rgb = mInfo->width * BPP;
        dsiObj->videoSizeCfg.hfp = (mInfo->hFrontPorch * BPP) - 6U;
        dsiObj->videoSizeCfg.blkLinePulsePacket = (horzTotal * BPP) - 20U - dsiObj->videoSizeCfg.hsa;

Do you have other idea, what we can check and what might be wrong?

Best regards,

Milena

  • Your question has been initially assigned to Mark

  • Additionally we have checked registers for horizontal and vertical position, and are not changing, when the use cases is running:

    Run #1:
    
    root@j784s4-evm:~#  devmem2 0x048000EC
    /dev/mem opened.
    Memory mapped at address 0xffff961ab000.
    Read at address  0x048000EC (0xffff961ab0ec): 0x000001C3
    root@j784s4-evm:~#  devmem2 0x048000EC
    /dev/mem opened.
    Memory mapped at address 0xffffa17f7000.
    Read at address  0x048000EC (0xffffa17f70ec): 0x000001C3
    root@j784s4-evm:~#  devmem2 0x048000EC
    /dev/mem opened.
    Memory mapped at address 0xffff87405000.
    Read at address  0x048000EC (0xffff874050ec): 0x000001C3
    root@j784s4-evm:~# devmem2 0x048000E8
    /dev/mem opened.
    Memory mapped at address 0xffffbdedd000.
    Read at address  0x048000E8 (0xffffbdedd0e8): 0x00000000
    root@j784s4-evm:~# devmem2 0x048000E8
    /dev/mem opened.
    Memory mapped at address 0xffff94013000.
    Read at address  0x048000E8 (0xffff940130e8): 0x00000000
    root@j784s4-evm:~# devmem2 0x048000E8
    /dev/mem opened.
    Memory mapped at address 0xffffb4736000.
    Read at address  0x048000E8 (0xffffb47360e8): 0x00000000
    root@j784s4-evm:~# devmem2 0x048000E8
    /dev/mem opened.
    Memory mapped at address 0xffffacd39000.
    Read at address  0x048000E8 (0xffffacd390e8): 0x00000000
    root@j784s4-evm:~#
    
    
    
    
    Run #2
    login as: root
    root@j784s4-evm:~# devmem2 0x048000E8
    /dev/mem opened.
    Memory mapped at address 0xffffb12af000.
    Read at address  0x048000E8 (0xffffb12af0e8): 0x00000000
    root@j784s4-evm:~#  devmem2 0x048000EC
    /dev/mem opened.
    Memory mapped at address 0xffff8caa0000.
    Read at address  0x048000EC (0xffff8caa00ec): 0x00000143
    root@j784s4-evm:~#  devmem2 0x048000EC
    /dev/mem opened.
    Memory mapped at address 0xffff8f611000.
    Read at address  0x048000EC (0xffff8f6110ec): 0x00000143
    root@j784s4-evm:~#  devmem2 0x048000EC
    /dev/mem opened.
    Memory mapped at address 0xffff9cdd7000.
    Read at address  0x048000EC (0xffff9cdd70ec): 0x00000143
    root@j784s4-evm:~#
    

    We have also tried changes as suggested here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1438164/processor-sdk-j721s2-dsi0-interface-output-failed-when-run-vision-app/5550140?tisearch=e2e-sitesearch&keymatch=DPHY%2520AND%2520PLL%2520AND%2520LOCK#5550140 

    the number of lanes from 4 to 2, and increasing lane speed by 2,  but same behavior present.

    Below is the full log for 2 lanes (VFP is set to 32)., we have also tried setting to 1 and VFP-1 as suggested, but same behavior still.

    /cfs-file/__key/communityserver-discussions-components-files/791/log_2D00_display_2D00_2_2D00_lanes_5F00_NOK.txt

    Regards,

    Milena

  • Hi,

    These equations are given in the TRM, so please refer to TRM for details on these equations. 

    I see that DSI is reporting the missing HSYNC error, this means there is a mismatch in speed, so can you please share your complete parameters, including timing, number of lanes and lane speed parameters? Does your receiving device support fixed lane speed and/or fixed resolution? We might have to tune these parameters to fix missing hsync errors.

    Regards,

    Brijesh  

  • Hi Brijesh,

    Params are as follows, also for the serializer.

    Resolution is set explicitly to the serializer and other timing params (see below).

    Serializer has in the status registers, PCLK and VSync detected, while HSync and DE are not detected.

    TDA4 Serializer
    Number of Lanes 4 Set explicitly
    Lane speed 391.58Mbps (PCLK*BPP)/lane_num
    PCLK 65260000
    FPS 60
    Format RGB888 (24bpp) RGB888 (24bpp)
    TDA4 refClock 20Mhz N/A
    Htot 1420
    Hactive 1280 Set explicitly to 1280
    Hfp 100 Set explicitly to 100
    Hsw 20 Set explicitly to 20
    Hbp 20 Set explicitly to 20
    Vtot 766
    Vactive 720 Set explicitly to 720
    Vfp 32 Set explicitly to 32
    Vsw 4 Set explicitly to 4
    Vbp 10 Set explicitly to 10
    Packet Type Blanking  (default) Set explicitly to blanking 
    Burst mode Non burst with sync pulses Set explicitly to Non burst with sync pulses
    EOTP disabled(default) Set explicitly to disabled

    Please check if we properly recognized the default TDA4 setup

    Additionally, printout of the registers:

    root@j784s4-evm:~# devmem2 0x048000B0
    /dev/mem opened.
    Memory mapped at address 0xffff94e99000.
    Read at address  0x048000B0 (0xffff94e990b0): 0x80B8FE00
    root@j784s4-evm:~#
    
    root@j784s4-evm:~# devmem2 0x04800004
    /dev/mem opened.
    Memory mapped at address 0xffff8c6bf000.
    Read at address  0x04800004 (0xffff8c6bf004): 0x00000025
    root@j784s4-evm:~#
    
    root@j784s4-evm:~# devmem2 0x048000B4
    /dev/mem opened.
    Memory mapped at address 0xffff8926f000.
    Read at address  0x048000B4 (0xffff8926f0b4): 0x00020284
    
    root@j784s4-evm:~# devmem2 0x048000B8
    /dev/mem opened.
    Memory mapped at address 0xffff96fa2000.
    Read at address  0x048000B8 (0xffff96fa20b8): 0x000002D0
    root@j784s4-evm:~# devmem2 0x048000C0
    /dev/mem opened.
    Memory mapped at address 0xffff9b5d0000.
    Read at address  0x048000C0 (0xffff9b5d00c0): 0x0030002E
    root@j784s4-evm:~# devmem2 0x048000C4
    /dev/mem opened.
    Memory mapped at address 0xffffb8695000.
    Read at address  0x048000C4 (0xffffb86950c4): 0x01260F00
    root@j784s4-evm:~# devmem2 0x048000CC
    /dev/mem opened.
    Memory mapped at address 0xffffbb1f1000.
    Read at address  0x048000CC (0xffffbb1f10cc): 0x00000000
    root@j784s4-evm:~# devmem2 0x048000D0
    /dev/mem opened.
    Memory mapped at address 0xffffaaf8c000.
    Read at address  0x048000D0 (0xffffaaf8c0d0): 0x00001090
    root@j784s4-evm:~# devmem2 0x048000D8
    /dev/mem opened.
    Memory mapped at address 0xffff9062d000.
    Read at address  0x048000D8 (0xffff9062d0d8): 0x00000000
    root@j784s4-evm:~# devmem2 0x048000DC
    /dev/mem opened.
    Memory mapped at address 0xffff96c23000.
    Read at address  0x048000DC (0xffff96c230dc): 0x03500419
    root@j784s4-evm:~# devmem2 0x048000F0
    /dev/mem opened.
    Memory mapped at address 0xffff91d40000.
    Read at address  0x048000F0 (0xffff91d400f0): 0x00000004
    root@j784s4-evm:~#
    
    root@j784s4-evm:~# devmem2 0x04800008
    /dev/mem opened.
    Memory mapped at address 0xffff9e704000.
    Read at address  0x04800008 (0xffff9e704008): 0x00003C17
    root@j784s4-evm:~#
    

    Printout from the driver:

    [MCU2_0]     17.558954 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     17.559005 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     17.559045 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0]     17.559138 s: **********************lane_speed: 391580*******************
    [MCU2_0]     17.559176 s: **********************refClkKHz: 20000*******************
    [MCU2_0]     17.559213 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0]     17.559259 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0]     17.559297 s: **********************tempResult: 313*******************
    
    [MCU2_0]     17.560230 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     17.560268 s: ******************mInfo.vfp: 32***************
    [MCU2_0]     17.560301 s: ******************mInfo.vbp: 10***************
    [MCU2_0]     17.560333 s: ******************mInfo.vsa: 4***************
    [MCU2_0]     17.560364 s: ******************mInfo.hsa: 20***************
    [MCU2_0]     17.560396 s: ******************mInfo.hbp: 20***************
    [MCU2_0]     17.560427 s: ******************mInfo.hfp: 100***************
    [MCU2_0]     17.560462 s: ******************mInfo.pixelClock: 65260000***************
    
    [MCU2_0]     17.560514 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     17.560550 s: ******************horzTotal: 1420***************
    [MCU2_0]     17.560585 s: ******************dsiObj->videoSizeCfg.vact: 720***************
    [MCU2_0]     17.560624 s: ******************dsiObj->videoSizeCfg.vfp: 32***************
    [MCU2_0]     17.560662 s: ******************dsiObj->videoSizeCfg.vbp: 10***************
    [MCU2_0]     17.560700 s: ******************dsiObj->videoSizeCfg.vsa: 4***************
    [MCU2_0]     17.560738 s: ******************dsiObj->videoSizeCfg.hsa: 46***************
    [MCU2_0]     17.560779 s: ******************dsiObj->videoSizeCfg.hbp: 48***************
    [MCU2_0]     17.560818 s: ******************dsiObj->videoSizeCfg.rgb: 3840***************
    [MCU2_0]     17.560856 s: ******************dsiObj->videoSizeCfg.hfp: 294***************
    [MCU2_0]     17.560897 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 4194***************
    [MCU2_0]     17.560946 s: ******************mInfo.vfp: 32***************
    [MCU2_0]     17.560977 s: ******************mInfo.vbp: 10***************
    [MCU2_0]     17.561008 s: ******************mInfo.vsa: 4***************
    [MCU2_0]     17.561039 s: ******************mInfo.hsa: 20***************
    [MCU2_0]     17.561070 s: ******************mInfo.hbp: 20***************
    [MCU2_0]     17.561101 s: ******************mInfo.hfp: 100***************
    [MCU2_0]     17.561135 s: ******************mInfo.pixelClock: 65260000***************

    Best regards,

    Milena

  • hi Milena,

    Can you change the timing parameters to below? 

    Width = 1280

    Height = 720

    HFP = 100

    HBP = 100

    HSL = 20

    VFP = 16

    FBP = 4

    VSL = 10

    FPS = 60

    Pixel clock = 67.5MHz

    Num Lanes = 4

    Lane speed = 405000000

    With this change, hsync error should go away..

    This assumes that TDA4 is receiving 20MHz as sysclk. 

    Regards,

    Brijesh

  • Hi Brijesh,

    We have tested above mentioned params.

    We do have same behavior, HSync is not detected.

    Above params are applied on both TDA4 and serializer.

    Below is snippet from TDA4 logs:

    [MCU2_0]     16.902602 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.902656 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.902696 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0]     16.902792 s: **********************lane_speed: 405000*******************
    [MCU2_0]     16.902831 s: **********************refClkKHz: 20000*******************
    [MCU2_0]     16.902876 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0]     16.902916 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0]     16.902953 s: **********************tempResult: 324*******************
    
    [MCU2_0]     16.903885 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     16.903921 s: ******************mInfo.vfp: 16***************
    [MCU2_0]     16.903952 s: ******************mInfo.vbp: 4***************
    [MCU2_0]     16.903985 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.904016 s: ******************mInfo.hsa: 20***************
    [MCU2_0]     16.904048 s: ******************mInfo.hbp: 100***************
    [MCU2_0]     16.904080 s: ******************mInfo.hfp: 100***************
    [MCU2_0]     16.904116 s: ******************mInfo.pixelClock: 67500000***************
    
    [MCU2_0]     16.904168 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     16.904205 s: ******************horzTotal: 1500***************
    [MCU2_0]     16.904240 s: ******************dsiObj->videoSizeCfg.vact: 720***************
    [MCU2_0]     16.904279 s: ******************dsiObj->videoSizeCfg.vfp: 16***************
    [MCU2_0]     16.904317 s: ******************dsiObj->videoSizeCfg.vbp: 4***************
    [MCU2_0]     16.904355 s: ******************dsiObj->videoSizeCfg.vsa: 10***************
    [MCU2_0]     16.904393 s: ******************dsiObj->videoSizeCfg.hsa: 46***************
    [MCU2_0]     16.904431 s: ******************dsiObj->videoSizeCfg.hbp: 288***************
    [MCU2_0]     16.904470 s: ******************dsiObj->videoSizeCfg.rgb: 3840***************
    [MCU2_0]     16.904509 s: ******************dsiObj->videoSizeCfg.hfp: 294***************
    [MCU2_0]     16.904550 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 4434***************
    [MCU2_0]     16.904579 s:
    [MCU2_0]     16.904599 s: ******************mInfo.vfp: 16***************
    [MCU2_0]     16.904630 s: ******************mInfo.vbp: 4***************
    [MCU2_0]     16.904661 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.904692 s: ******************mInfo.hsa: 20***************
    [MCU2_0]     16.904724 s: ******************mInfo.hbp: 100***************
    [MCU2_0]     16.904755 s: ******************mInfo.hfp: 100***************
    [MCU2_0]     16.904791 s: ******************mInfo.pixelClock: 67500000***************

    Best regards,

    Milena

  • Hi Milena,

    Can you read the value at the offset 0x048000F0? It should say now 0x1, which means DSI is outputting data. 

    Regards,

    Brijesh

  • Hi Brijesh,

    It is still 0x4 (ERR_MISSING_HSYNC). 

    root@j784s4-evm:~# devmem2 0x048000F0
    /dev/mem opened.
    Memory mapped at address 0xffff7fb2b000.
    Read at address 0x048000F0 (0xffff7fb2b0f0): 0x00000004
    root@j784s4-evm:~#

    Regards,

    Milena

  • Hi Milena,

    Could you also print the value of dphyTxFbDiv? It should come around 81. 

    Regards,

    Brijesh

  • Hi Brijesh,

    I printed it explicitly(for any case), but it same as tempResult in previous log.

    These are printouts from the dssdctrlCalcDsiParams function, should we print it somewhere else?

    Value is 324, which is inline with code formula:

    (lane_speed_in_kbps * 2 * dphyTxIpDiv * dphyTxOpDiv) / refClkKHz

    (405000 * 2 * 2 * 4) / 20000 = 324

    ----------------------------------------------------------------------------------------

    Note: from Code:

    [MCU2_0] 17.331244 s: **********************dsiObj->dphyTxIpDiv: 2******************* OK
    Div by 2, if refer clock value is between 19.2MHz to 38.4MHz range

    [MCU2_0] 17.331284 s: **********************dsiObj->dphyTxOpDiv: 4******************* OK
    Div by 4, if lane speed is in between 620 Mbps to 320Mbps range

    ----------------------------------------------------------------------------------------

    [MCU2_0] 17.425929 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0] 17.425979 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0] 17.426019 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0] 17.426112 s: **********************lane_speed: 405000*******************
    [MCU2_0] 17.426153 s: **********************refClkKHz: 20000*******************
    [MCU2_0] 17.426199 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0] 17.426239 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0] 17.426277 s: **********************tempResult: 324*******************
    [MCU2_0] 17.426315 s: **********************dsiObj->dphyTxFbDiv: 324*******************

    Regards,

    Milena

  • Hi Brijesh,

    Any thoughts about the above?

    Additionally, we have also noticed that some of the values are just assigned in the dss_dctrDsi.c file. 

    Do some of these values need to be updated as well?

    Function: dssDctrlInitPhyConfig

    drvObj->phyCfg.waitBurstTime = 15; /* TODO: How to calculate waitBurstTime */

    Function: dssDctrlSetDphyConfiguration

            /* TODO: How to calculate these parameters */
            dsiObj->dphyCfg.clkDivisionRatio = 0xBU;
            dsiObj->dphyCfg.hstxTimeout = 0xAFFFU;
            dsiObj->dphyCfg.lprxTimeout = 0x3FFFFU;
            dsiObj->dphyCfg.clkLaneUlpTimeout = 0x105U;
            dsiObj->dphyCfg.dataLaneUlpTimeout = 0x1D5U;

    Function: dssDctrlUpdateVideoModeConfig 

    /* TODO: How to calculate this params */
        dsiObj->videoModeCfg.regWakeupTime = 0x1A8U; // any non-zero value, value from other tests

    Best regards,

    Milena

  • Hi Milena,

    We dont need to change any other parameters. 

    One question, are we sure that the input frequency in 20MHz for the PHY? 

    Regards,

    Brijesh 

  • Hi Brijesh,

    Our board is 20Mhz - MCU_BOOTMODE[2:0] are HW strapped to the "001" which should be 20Mhz.

    And are reading from code 20000 as refClkKHz .

    PMLIBClkRateGet(TISCI_DEV_DPHY_TX0,
                TISCI_DEV_DPHY_TX0_DPHY_REF_CLK,
                &refClkKHz);
    refClkKHz = refClkKHz/1000;

    Best regards,

    Milena

  • Additionally, just as info, when we enable the pattern generator on the serializer, with the same timing params that you suggested above, pattern is visible on the display.

    If it is more convenient, or easier to debug, we can have a call (if it is an option).

    Milena

  • Hi Milena,

    But if the reference clock is matching and its 20MHz, there should not be missing hsync error with the FbDiv value set to 324. The timing is now matching and there should not be any error. So can we please reconfirm 20MHz reference clock? 

    Regards,

    Brijesh

  • Hi Brijesh,

    We have double checked with HW team, and we do have 20Mhz on WKUP_OSC0, and 26MHz on OSC1.

    Also we checked registers for CTRL_MMR_CFG0_DPHY0_CLKSEL, see below.

    DPHY0_CLKSEL[1:0] is set to HFOSC_0.

    root@j784s4-evm:~# devmem2 0x00108310
    /dev/mem opened.
    Memory mapped at address 0xffff81584000.
    Read at address  0x00108310 (0xffff81584310): 0x00000000
    root@j784s4-evm:~# devmem2 0x00108314
    /dev/mem opened.
    Memory mapped at address 0xffffb1bdd000.
    Read at address  0x00108314 (0xffffb1bdd314): 0x00000000
    

    Do you have something else in mind for reconfirming reference clock ? 

    Best regards,

    Milena

  • Hi Brijesh,

    We have measured with the scope ref frequency. It is stable and is little bit below 20MHz.

    We have tested multiple values for the dsiObj->dphyTxFbDiv (323 to 337).

    TDA4 always returns 0x04 in register: 0x048000F0

    Serializer seems to have least reported errors when the dphyTxFbDiv  is set to 325.

    Any ideas from your side?

    Best regards,

    Milena

  • Hi Milena,

    FbDiv is typically the only parameter which potentially causes this hsync error. I am not aware of any other parameter. 

    But it should not be configured with any value. It has dependency on the input reference clock and input/output divisors. So what we used earlier from the calculation is the correct value. 

    We will need to check in the specs if there is anything else that can cause this error. 

    Is it possible to try some different resolution and see atleast first this missing hsync error goes way? 

    Regards,

    Brijesh

  • Hello Brijesh,

    We can test other resolution for test purposes, serializer supports range of resolutions, display will not probably work, but for test purposes connection between ser and tda4 can be tested.

    Do you have some specific resolution in your mind? 

    Best regards,

    Milena

  • Hi Milena,

    Yes, can we test some lower resolution like 720p or even lower like VGA or something? 

    Regards,

    Brijesh

  • Hello Brijesh,

    Additional question:

    We have found following statement in the TRM, page 392 for TDA4VH.

    Supported input reference clock frequencies to the PLL are 19.2/24/25/26 MHz only.

    We are using 20MHz. Does this means that this frequency is not supported in our use case, and we should switch to the one from the list?

    Best regards,

    Milena

  • Hello Brijesh,

    We have tried to use different clock for DPHY- OSC1 , which is 26MHz at out side.

    We wrote in the register before dss and fvid2 initialization in the vision_apps/ app_init .

    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_DPHY0_CLKSEL, 0x1); 

    With devmem2 we have confirmed that the register is OK  - set to 1

    root@j784s4-evm:~# devmem2 0x00108310
    /dev/mem opened.
    Memory mapped at address 0xffffb28e6000.
    Read at address  0x00108310 (0xffffb28e6310): 0x00000001
    root@j784s4-evm:~#
    

    With this, DSS does not initialize succesfully.

    It fails in the  dssDctrlEnableDsiDatapath  function which calls  DSITX_CheckLanesState function which return status: 5 (CDN_EIO).

    Are we missing something in order to switch to the OSC1? 

    Best regards,

    Milena

  • Hi Brijesh,

    Additionally we have tested with smaller resolution - for any case.

    But behavior on TDA4 side is same, and additionally for this resolution serializer raised global error flag compared to the previous tests.

    Log is below (you can see exact params tested). Reading the status register with devmem2 gives 0x4 (HSYNC_ERROR). 

    [MCU2_0]     14.725209 s: DSS: SoC init ... Done !!!
    [MCU2_0]     14.725226 s: DSS: Board init ... !!!
    [MCU2_0]     14.725243 s: DSS: Configuring LA080WH1 Display!
    [MCU2_0]     17.604465 s: DSS: Configuring LA080WH1 Done !!!
    [MCU2_0]     17.604490 s: DSS: Configuring MAX96755F Serializer!
    [MCU2_0]     17.610233 s: DSS: Configuring MAX96755F Done !!!
    [MCU2_0]     17.614930 s: DSS: Board init ... Done !!!
    [MCU2_0]     17.615767 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     17.615821 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     17.615861 s: ******************dsiObj->dphyTxRate: 66***************
    [MCU2_0]     17.616072 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1157:
    [MCU2_0]     17.616100 s: Should enter here
    [MCU2_0]     17.616128 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 559:
    [MCU2_0]     17.616151 s: status value1: 0
    [MCU2_0]     17.616175 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 566:
    [MCU2_0]     17.616197 s: status value2: 0
    [MCU2_0]     17.616221 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 572:
    [MCU2_0]     17.616245 s: status value3: 0
    [MCU2_0]     17.616273 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 578:
    [MCU2_0]     17.616296 s: status value4: 0
    [MCU2_0]     17.616560 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 584:
    [MCU2_0]     17.616583 s: status value5: 0
    [MCU2_0]     17.616604 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 590:
    [MCU2_0]     17.616626 s: status value6: 0
    [MCU2_0]     17.616651 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 596:
    [MCU2_0]     17.616673 s: status value7: 0
    [MCU2_0]     17.616692 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 602:
    [MCU2_0]     17.616715 s: status value8: 0
    [MCU2_0]     17.616757 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     17.616804 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     17.616852 s: ***********************vidMode->syncPulseActive in getter: false***********************
    [MCU2_0]     17.616901 s: ***********************vidMode->burstMode u getter: false***********************
    [MCU2_0]     17.616936 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     17.616977 s: ******************mInfo.vfp: 11***************
    [MCU2_0]     17.617009 s: ******************mInfo.vbp: 31***************
    [MCU2_0]     17.617041 s: ******************mInfo.vsa: 2***************
    [MCU2_0]     17.617072 s: ******************mInfo.hsa: 96***************
    [MCU2_0]     17.617104 s: ******************mInfo.hbp: 48***************
    [MCU2_0]     17.617136 s: ******************mInfo.hfp: 16***************
    [MCU2_0]     17.617170 s: ******************mInfo.pixelClock: 25150000***************
    [MCU2_0]     17.617197 s: ******************Udje ovde***************
    [MCU2_0]     17.617223 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     17.617260 s: ******************horzTotal: 800***************
    [MCU2_0]     17.617295 s: ******************dsiObj->videoSizeCfg.vact: 480***************
    [MCU2_0]     17.617333 s: ******************dsiObj->videoSizeCfg.vfp: 11***************
    [MCU2_0]     17.617372 s: ******************dsiObj->videoSizeCfg.vbp: 31***************
    [MCU2_0]     17.617410 s: ******************dsiObj->videoSizeCfg.vsa: 2***************
    [MCU2_0]     17.617448 s: ******************dsiObj->videoSizeCfg.hsa: 274***************
    [MCU2_0]     17.617487 s: ******************dsiObj->videoSizeCfg.hbp: 132***************
    [MCU2_0]     17.617525 s: ******************dsiObj->videoSizeCfg.rgb: 1920***************
    [MCU2_0]     17.617564 s: ******************dsiObj->videoSizeCfg.hfp: 42***************
    [MCU2_0]     17.617605 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 2106***************
    [MCU2_0]     17.617633 s:
    [MCU2_0]     17.617654 s: ******************mInfo.vfp: 11***************
    [MCU2_0]     17.617685 s: ******************mInfo.vbp: 31***************
    [MCU2_0]     17.617716 s: ******************mInfo.vsa: 2***************
    [MCU2_0]     17.617747 s: ******************mInfo.hsa: 96***************
    [MCU2_0]     17.617778 s: ******************mInfo.hbp: 48***************
    [MCU2_0]     17.617809 s: ******************mInfo.hfp: 16***************
    [MCU2_0]     17.617842 s: ******************mInfo.pixelClock: 25150000***************
    [MCU2_0]     17.617893 s: ***********************vidMode->burstMode in setter: false***********************
    [MCU2_0]     17.617945 s: ***********************vidMode->syncPulseActive in setter: true***********************
    [MCU2_0]     17.617981 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 608:
    [MCU2_0]     17.618003 s: status value9: 0
    [MCU2_0]     17.618038 s: dssDctrlEnableDsiLinkAndPath 1117 ******************status: 0***************
    [MCU2_0]     17.618086 s: ***********************config->dispEotGen u getter: false***********************
    [MCU2_0]     17.618131 s: ***********************config->hostEotGen u getter: false***********************
    [MCU2_0]     17.618180 s: ***********************config->dispEotGen in setter: false***********************
    [MCU2_0]     17.618227 s: ***********************config->hostEotGen in setter: false***********************
    [MCU2_0]     17.618274 s: dssDctrlEnableDsiDatapath 1155 ******************status: 0***************
    [MCU2_0]     17.618320 s: DSITX_WaitForPllLock 1096 ******************result: 0***************
    [MCU2_0]     17.618363 s: dssDctrlEnableDsiDatapath 1161 ******************status: 0***************
    [MCU2_0]     17.618407 s: dssDctrlEnableDsiDatapath 1168 ******************status: 0***************
    [MCU2_0]     17.618452 s: dssDctrlEnableDsiLinkAndPath 1121 ******************status: 0***************
    [MCU2_0]     17.618483 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 614:
    [MCU2_0]     17.618505 s: status value10: 0
    [MCU2_0]     17.618527 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 620:
    [MCU2_0]     17.618549 s: status value11: 0
    [MCU2_0]     17.618568 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1161:
    [MCU2_0]     17.618590 s: Retval value1: 0

    Can you please check this statement from the TRM?  We want to double check before making HW changes, and are not able as described above to switch to OSC1 as expected.

    We have found following statement in the TRM, page 392 for TDA4VH.

    Supported input reference clock frequencies to the PLL are 19.2/24/25/26 MHz only.

    Milena

  • Hi Milena,

    Supported input reference clock frequencies to the PLL are 19.2/24/25/26 MHz only.

    This is strange, i was not aware of this and need to check with the HW team. 

    But yes there is few more clock sources possible for DSI input clock, and one of them is OSC1 clock. Instead of directly configuring it in the register, can you please try using SciClient interface to change clock source for DPHY and see if it helps?

    Regards,

    Brijesh

  • Hi Brijesh,

    We have performed HW change, and populated 26Mhz  crystal instead of 20MHz. (mcu_bootmode pins set accordingly).

    From the logs I see that we have exact same behavior as with the 20MHz.

    Log with the params, for reference below. It is visible that refClk i set to 26Mhz.

    Additionally we have tested serializer pattern again in this environment and it is working, as earlier.

    Any ideas, how we can proceed?

    [MCU2_0]     14.323566 s: DSS: SoC init ... Done !!!
    [MCU2_0]     14.323583 s: DSS: Board init ... !!!
    [MCU2_0]     14.323601 s: DSS: Configuring LA080WH1 Display!
    [MCU2_0]     16.538866 s: DSS: Configuring LA080WH1 Done !!!
    [MCU2_0]     16.538892 s: DSS: Configuring MAX96755F Serializer!
    [MCU2_0]     16.549190 s: DSS: Configuring MAX96755F Done !!!
    [MCU2_0]     16.553908 s: DSS: Board init ... Done !!!
    [MCU2_0]     16.554747 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.554796 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.554838 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0]     16.554933 s: **********************lane_speed: 405000*******************
    [MCU2_0]     16.554972 s: **********************refClkKHz: 26000*******************
    [MCU2_0]     16.555010 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0]     16.555049 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0]     16.555086 s: **********************tempResult: 249*******************
    [MCU2_0]     16.555130 s: **********************dsiObj->dphyTxFbDiv: 249*******************
    [MCU2_0]     16.555286 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1157: 
    [MCU2_0]     16.555313 s: Should enter here
    [MCU2_0]     16.555344 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 542: 
    [MCU2_0]     16.555366 s: status value1: 0
    [MCU2_0]     16.555390 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 549: 
    [MCU2_0]     16.555412 s: status value2: 0
    [MCU2_0]     16.555437 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 555: 
    [MCU2_0]     16.555460 s: status value3: 0
    [MCU2_0]     16.555488 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 561: 
    [MCU2_0]     16.555511 s: status value4: 0
    [MCU2_0]     16.555676 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 567: 
    [MCU2_0]     16.555698 s: status value5: 0
    [MCU2_0]     16.555718 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 573: 
    [MCU2_0]     16.555740 s: status value6: 0
    [MCU2_0]     16.555764 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 579: 
    [MCU2_0]     16.555786 s: status value7: 0
    [MCU2_0]     16.555804 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 585: 
    [MCU2_0]     16.555827 s: status value8: 0
    [MCU2_0]     16.555871 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     16.555917 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     16.555965 s: ***********************vidMode->syncPulseActive in getter: false***********************
    [MCU2_0]     16.556013 s: ***********************vidMode->burstMode u getter: false***********************
    [MCU2_0]     16.556049 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     16.556086 s: ******************mInfo.vfp: 16***************
    [MCU2_0]     16.556118 s: ******************mInfo.vbp: 4***************
    [MCU2_0]     16.556149 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.556181 s: ******************mInfo.hsa: 20***************
    [MCU2_0]     16.556212 s: ******************mInfo.hbp: 100***************
    [MCU2_0]     16.556244 s: ******************mInfo.hfp: 100***************
    [MCU2_0]     16.556279 s: ******************mInfo.pixelClock: 67500000***************
    
    [MCU2_0]     16.556332 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     16.556369 s: ******************horzTotal: 1500***************
    [MCU2_0]     16.556404 s: ******************dsiObj->videoSizeCfg.vact: 720***************
    [MCU2_0]     16.556443 s: ******************dsiObj->videoSizeCfg.vfp: 16***************
    [MCU2_0]     16.556481 s: ******************dsiObj->videoSizeCfg.vbp: 4***************
    [MCU2_0]     16.556519 s: ******************dsiObj->videoSizeCfg.vsa: 10***************
    [MCU2_0]     16.556557 s: ******************dsiObj->videoSizeCfg.hsa: 46***************
    [MCU2_0]     16.556597 s: ******************dsiObj->videoSizeCfg.hbp: 288***************
    [MCU2_0]     16.556636 s: ******************dsiObj->videoSizeCfg.rgb: 3840***************
    [MCU2_0]     16.556675 s: ******************dsiObj->videoSizeCfg.hfp: 294***************
    [MCU2_0]     16.556716 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 4434***************
    [MCU2_0]     16.556745 s: 
    [MCU2_0]     16.556766 s: ******************mInfo.vfp: 16***************
    [MCU2_0]     16.556796 s: ******************mInfo.vbp: 4***************
    [MCU2_0]     16.556827 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.556859 s: ******************mInfo.hsa: 20***************
    [MCU2_0]     16.556890 s: ******************mInfo.hbp: 100***************
    [MCU2_0]     16.556921 s: ******************mInfo.hfp: 100***************
    [MCU2_0]     16.556955 s: ******************mInfo.pixelClock: 67500000***************
    [MCU2_0]     16.557007 s: ***********************vidMode->burstMode in setter: false***********************
    [MCU2_0]     16.557055 s: ***********************vidMode->syncPulseActive in setter: true***********************
    [MCU2_0]     16.557091 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 591: 
    [MCU2_0]     16.557113 s: status value9: 0
    [MCU2_0]     16.557151 s: ***********************config->dispEotGen u getter: false***********************
    [MCU2_0]     16.557198 s: ***********************config->hostEotGen u getter: false***********************
    [MCU2_0]     16.557246 s: ***********************config->dispEotGen in setter: false***********************
    [MCU2_0]     16.557294 s: ***********************config->hostEotGen in setter: false***********************
    [MCU2_0]     16.557353 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 597: 
    [MCU2_0]     16.557376 s: status value10: 0
    [MCU2_0]     16.557399 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 603: 
    [MCU2_0]     16.557422 s: status value11: 0
    [MCU2_0]     16.557441 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1161: 
    [MCU2_0]     16.557464 s: Retval value1: 0

    Best regards,

    Milena

  • Hello Milena,

    But now with 26MHz input clock, we would need to change the other parameters.. Pixel clock becomes 68.25MHz and lane speed is now 409500KHz, FbDiv should be 252. and Timing parameters needs to be changed as below.

    Width = 1280

    hfp = 8

    hsl = 2

    hbp = 10

    Height = 720

    VFP = 16

    FBP = 129

    VSL = 10

    Regards,

    Brijesh

  • HI Brijesh,

    With this values we do not have successful initialization of DSS.

    I suppose issue is in the dss_dctrDsi.c: 

     dsiObj->videoSizeCfg.hsa = (mInfo->hSyncLen * BPP) - 14U;

    videoSizeCfg.hsa =  2 *3 -14 = -5 which is negative, or very large value.

    Shall we adapt values such that this becomes positive?

    Best regards,

    Milena

  • Hello Milena,

    Yes, can we interchange values of hfp and hsl? 

    Regards,

    Brijesh

  • Hi Brijesh,

    Still it fail sin the init.

    Full log of params below.

    Basically it fails in the: dssDctrlSetVideoConfig function.

    It fails at  DSITX_SetVideoSize, during check of params: DSITX_SetVideoSizeSF.

    [MCU2_0]     14.663659 s: DSS: SoC init ... Done !!!
    [MCU2_0]     14.663677 s: DSS: Board init ... !!!
    [MCU2_0]     14.663695 s: DSS: Configuring LA080WH1 Display!
    [MCU2_0]     16.878762 s: DSS: Configuring LA080WH1 Done !!!
    [MCU2_0]     16.878789 s: DSS: Configuring MAX96755F Serializer!
    [MCU2_0]     16.889088 s: DSS: Configuring MAX96755F Done !!!
    [MCU2_0]     16.893804 s: DSS: Board init ... Done !!!
    [MCU2_0]     16.894640 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.894690 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.894730 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0]     16.894828 s: **********************lane_speed: 405000*******************
    [MCU2_0]     16.894866 s: **********************refClkKHz: 26000*******************
    [MCU2_0]     16.894904 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0]     16.894943 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0]     16.894981 s: **********************tempResult: 249*******************
    [MCU2_0]     16.895022 s: **********************dsiObj->dphyTxFbDiv: 249*******************
    [MCU2_0]     16.895188 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1157: 
    [MCU2_0]     16.895217 s: Should enter here
    [MCU2_0]     16.895249 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 542: 
    [MCU2_0]     16.895272 s: status value1: 0
    [MCU2_0]     16.895298 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 549: 
    [MCU2_0]     16.895321 s: status value2: 0
    [MCU2_0]     16.895344 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 555: 
    [MCU2_0]     16.895367 s: status value3: 0
    [MCU2_0]     16.895395 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 561: 
    [MCU2_0]     16.895419 s: status value4: 0
    [MCU2_0]     16.895583 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 567: 
    [MCU2_0]     16.895605 s: status value5: 0
    [MCU2_0]     16.895627 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 573: 
    [MCU2_0]     16.895649 s: status value6: 0
    [MCU2_0]     16.895672 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 579: 
    [MCU2_0]     16.895694 s: status value7: 0
    [MCU2_0]     16.895713 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 585: 
    [MCU2_0]     16.895735 s: status value8: 0
    [MCU2_0]     16.895782 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     16.895828 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     16.895875 s: ***********************vidMode->syncPulseActive in getter: false***********************
    [MCU2_0]     16.895924 s: ***********************vidMode->burstMode u getter: false***********************
    [MCU2_0]     16.895959 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     16.895995 s: ******************mInfo.vfp: 16***************
    [MCU2_0]     16.896028 s: ******************mInfo.vbp: 129***************
    [MCU2_0]     16.896059 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.896091 s: ******************mInfo.hsa: 8***************
    [MCU2_0]     16.896122 s: ******************mInfo.hbp: 10***************
    [MCU2_0]     16.896154 s: ******************mInfo.hfp: 2***************
    [MCU2_0]     16.896188 s: ******************mInfo.pixelClock: 68250000***************
    
    [MCU2_0]     16.896240 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 525: 
    [MCU2_0]     16.896264 s: status dssDctrlValidateSupportedVpModes retVal : 0
    [MCU2_0]     16.896290 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     16.896328 s: ******************horzTotal: 1300***************
    [MCU2_0]     16.896364 s: ******************dsiObj->videoSizeCfg.vact: 720***************
    [MCU2_0]     16.896403 s: ******************dsiObj->videoSizeCfg.vfp: 16***************
    [MCU2_0]     16.896441 s: ******************dsiObj->videoSizeCfg.vbp: 129***************
    [MCU2_0]     16.896483 s: ******************dsiObj->videoSizeCfg.vsa: 10***************
    [MCU2_0]     16.896521 s: ******************dsiObj->videoSizeCfg.hsa: 10***************
    [MCU2_0]     16.896559 s: ******************dsiObj->videoSizeCfg.hbp: 18***************
    [MCU2_0]     16.896597 s: ******************dsiObj->videoSizeCfg.rgb: 3840***************
    [MCU2_0]     16.896636 s: ******************dsiObj->videoSizeCfg.hfp: 0***************
    [MCU2_0]     16.896677 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 3870***************
    [MCU2_0]     16.896705 s: 
    [MCU2_0]     16.896726 s: ******************mInfo.vfp: 16***************
    [MCU2_0]     16.896757 s: ******************mInfo.vbp: 129***************
    [MCU2_0]     16.896789 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.896820 s: ******************mInfo.hsa: 8***************
    [MCU2_0]     16.896851 s: ******************mInfo.hbp: 10***************
    [MCU2_0]     16.896883 s: ******************mInfo.hfp: 2***************
    [MCU2_0]     16.896916 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     16.896950 s: DSITX_SetVideoSize status 22 
    [MCU2_0]     16.896971 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 591: 
    [MCU2_0]     16.896994 s: status value9: 22
    [MCU2_0]     16.897012 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 613: 
    [MCU2_0]     16.897035 s: status value12: -3
    [MCU2_0]     16.897055 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1161: 
    [MCU2_0]     16.897077 s: Retval value1: -3
    [MCU2_0]     16.897098 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1182: 
    [MCU2_0]     16.897121 s: Set VP parameters IOCTL failed
    [MCU2_0]     16.897172 s: DSS: ERROR: Dctrl default init failed !!!

    Regards,

    Milena

  • Hello Milena,

    Sorry, could not understand where it is failing. But i see that hfp is becoming 0. We need to split 20 pixels of blanking such that hsa, hbp and hfp not becoming 0. Can we set hsl to 8, hbp to 6 and hfp to 6 ?

    dsiObj->videoSizeCfg.hsa = (mInfo->hSyncLen * BPP) - 14U;
    dsiObj->videoSizeCfg.hbp = (mInfo->hBackPorch * BPP) - 12U;

    dsiObj->videoSizeCfg.hfp = (mInfo->hFrontPorch * BPP) - 6U;

    Regards,

    Brijesh

  • Hi Brijesh,

    We have tested params: HFP:10, HBP: 5, HSL 5.

    TRM suggests following, and the above are min values.

    However it still fails with the same error:

    [MCU2_0]     14.640129 s: DSS: SoC init ... Done !!!
    [MCU2_0]     14.640146 s: DSS: Board init ... !!!
    [MCU2_0]     14.640163 s: DSS: Configuring LA080WH1 Display!
    [MCU2_0]     16.855179 s: DSS: Configuring LA080WH1 Done !!!
    [MCU2_0]     16.855206 s: DSS: Configuring MAX96755F Serializer!
    [MCU2_0]     16.865502 s: DSS: Configuring MAX96755F Done !!!
    [MCU2_0]     16.870220 s: DSS: Board init ... Done !!!
    [MCU2_0]     16.871052 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.871103 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.871144 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0]     16.871240 s: **********************lane_speed: 409500*******************
    [MCU2_0]     16.871279 s: **********************refClkKHz: 26000*******************
    [MCU2_0]     16.871317 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0]     16.871355 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0]     16.871393 s: **********************tempResult: 252*******************
    [MCU2_0]     16.871435 s: **********************dsiObj->dphyTxFbDiv: 252*******************
    [MCU2_0]     16.871593 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1157: 
    [MCU2_0]     16.871621 s: Should enter here
    [MCU2_0]     16.871653 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 542: 
    [MCU2_0]     16.871677 s: status value1: 0
    [MCU2_0]     16.871701 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 549: 
    [MCU2_0]     16.871723 s: status value2: 0
    [MCU2_0]     16.871747 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 555: 
    [MCU2_0]     16.871770 s: status value3: 0
    [MCU2_0]     16.871800 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 561: 
    [MCU2_0]     16.871822 s: status value4: 0
    [MCU2_0]     16.871987 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 567: 
    [MCU2_0]     16.872009 s: status value5: 0
    [MCU2_0]     16.872030 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 573: 
    [MCU2_0]     16.872052 s: status value6: 0
    [MCU2_0]     16.872077 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 579: 
    [MCU2_0]     16.872099 s: status value7: 0
    [MCU2_0]     16.872118 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 585: 
    [MCU2_0]     16.872141 s: status value8: 0
    [MCU2_0]     16.872187 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     16.872232 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     16.872281 s: ***********************vidMode->syncPulseActive in getter: false***********************
    [MCU2_0]     16.872330 s: ***********************vidMode->burstMode u getter: false***********************
    [MCU2_0]     16.872366 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     16.872402 s: ******************mInfo.vfp: 16***************
    [MCU2_0]     16.872434 s: ******************mInfo.vbp: 129***************
    [MCU2_0]     16.872466 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.872497 s: ******************mInfo.hsa: 5***************
    [MCU2_0]     16.872528 s: ******************mInfo.hbp: 5***************
    [MCU2_0]     16.872559 s: ******************mInfo.hfp: 10***************
    [MCU2_0]     16.872594 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     16.872622 s: ******************Udje ovde***************
    [MCU2_0]     16.872647 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 525: 
    [MCU2_0]     16.872671 s: status dssDctrlValidateSupportedVpModes retVal : 0
    [MCU2_0]     16.872697 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     16.872735 s: ******************horzTotal: 1300***************
    [MCU2_0]     16.872771 s: ******************dsiObj->videoSizeCfg.vact: 720***************
    [MCU2_0]     16.872809 s: ******************dsiObj->videoSizeCfg.vfp: 16***************
    [MCU2_0]     16.872847 s: ******************dsiObj->videoSizeCfg.vbp: 129***************
    [MCU2_0]     16.872885 s: ******************dsiObj->videoSizeCfg.vsa: 10***************
    [MCU2_0]     16.872925 s: ******************dsiObj->videoSizeCfg.hsa: 1***************
    [MCU2_0]     16.872963 s: ******************dsiObj->videoSizeCfg.hbp: 3***************
    [MCU2_0]     16.873001 s: ******************dsiObj->videoSizeCfg.rgb: 3840***************
    [MCU2_0]     16.873040 s: ******************dsiObj->videoSizeCfg.hfp: 24***************
    [MCU2_0]     16.873081 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 3879***************
    [MCU2_0]     16.873109 s: 
    [MCU2_0]     16.873130 s: ******************mInfo.vfp: 16***************
    [MCU2_0]     16.873161 s: ******************mInfo.vbp: 129***************
    [MCU2_0]     16.873192 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.873224 s: ******************mInfo.hsa: 5***************
    [MCU2_0]     16.873255 s: ******************mInfo.hbp: 5***************
    [MCU2_0]     16.873286 s: ******************mInfo.hfp: 10***************
    [MCU2_0]     16.873320 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     16.873353 s: DSITX_SetVideoSize status 22 
    [MCU2_0]     16.873374 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 591: 
    [MCU2_0]     16.873397 s: status value9: 22
    [MCU2_0]     16.873415 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 613: 
    [MCU2_0]     16.873437 s: status value12: -3
    [MCU2_0]     16.873456 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1161: 
    [MCU2_0]     16.873478 s: Retval value1: -3
    [MCU2_0]     16.873500 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1182: 
    [MCU2_0]     16.873522 s: Set VP parameters IOCTL failed
    [MCU2_0]     16.873574 s: DSS: ERROR: Dctrl default init failed !!!
    
    

    Can you check what are the param checks in this function? Since we do not have source code, and cannot find any other limitations in TRM regarding the params..

    Regards,

    Milena

  • Hi Milena,

    Since there are prints in this file, i am not sure where exact it is failing. can you please tell me the line from the code where it is failing?

    Regards,

    Brijesh

  • Hi Brijesh,

    My editor was stuck in referencing, I see code for the SanityFunctions..

    Basically we fail in the DSITX_VideoSizeSF

     if (obj->vbp > (0x3FU))
        {
            ret = CDN_EINVAL;
        }

    Will try with different VFP, VSL and VBP. Any suggestion what shpuld we take care of?

    My idea is to test: VFP: 82, VSL: 10, VBP:63

    Regards,

    Milena

  • Hi Milena,

    Essentially, we need to make sure that the total frame height is 875, so can you try to adjust the blanking accordingly, keeping vbp below 63? 

    Regards,

    Brijesh

  • Hi Brijesh,

    We tested with the above stated params, DSS init is OK now, but still we have same error during use-case execution.

    All of the params seems fine from the log, however state is 0x04 - HSYNC ERR.

    [MCU2_0]     13.910579 s: DSS: SoC init ... Done !!!
    [MCU2_0]     13.910598 s: DSS: Board init ... !!!
    [MCU2_0]     13.910615 s: DSS: Configuring LA080WH1 Display!
    [MCU2_0]     16.125610 s: DSS: Configuring LA080WH1 Done !!!
    [MCU2_0]     16.125637 s: DSS: Configuring MAX96755F Serializer!
    [MCU2_0]     16.135925 s: DSS: Configuring MAX96755F Done !!!
    [MCU2_0]     16.140662 s: DSS: Board init ... Done !!!
    [MCU2_0]     16.141509 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.141559 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     16.141599 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0]     16.141692 s: **********************lane_speed: 409500*******************
    [MCU2_0]     16.141734 s: **********************refClkKHz: 26000*******************
    [MCU2_0]     16.141773 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0]     16.141812 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0]     16.141855 s: **********************tempResult: 252*******************
    [MCU2_0]     16.141893 s: **********************dsiObj->dphyTxFbDiv: 252*******************
    [MCU2_0]     16.142057 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1157: 
    [MCU2_0]     16.142086 s: Should enter here
    [MCU2_0]     16.142118 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 542: 
    [MCU2_0]     16.142142 s: status value1: 0
    [MCU2_0]     16.142167 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 549: 
    [MCU2_0]     16.142191 s: status value2: 0
    [MCU2_0]     16.142217 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 555: 
    [MCU2_0]     16.142239 s: status value3: 0
    [MCU2_0]     16.142268 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 561: 
    [MCU2_0]     16.142291 s: status value4: 0
    [MCU2_0]     16.142456 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 567: 
    [MCU2_0]     16.142478 s: status value5: 0
    [MCU2_0]     16.142499 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 573: 
    [MCU2_0]     16.142521 s: status value6: 0
    [MCU2_0]     16.142548 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 579: 
    [MCU2_0]     16.142570 s: status value7: 0
    [MCU2_0]     16.142594 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 585: 
    [MCU2_0]     16.142616 s: status value8: 0
    [MCU2_0]     16.142656 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     16.142702 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     16.142749 s: ***********************vidMode->syncPulseActive in getter: false***********************
    [MCU2_0]     16.142798 s: ***********************vidMode->burstMode u getter: false***********************
    [MCU2_0]     16.142835 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     16.142873 s: ******************mInfo.vfp: 82***************
    [MCU2_0]     16.142904 s: ******************mInfo.vbp: 63***************
    [MCU2_0]     16.142936 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.142967 s: ******************mInfo.hsa: 5***************
    [MCU2_0]     16.142998 s: ******************mInfo.hbp: 5***************
    [MCU2_0]     16.143030 s: ******************mInfo.hfp: 10***************
    [MCU2_0]     16.143065 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     16.143118 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 525: 
    [MCU2_0]     16.143141 s: status dssDctrlValidateSupportedVpModes retVal : 0
    [MCU2_0]     16.143167 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     16.143203 s: ******************horzTotal: 1300***************
    [MCU2_0]     16.143238 s: ******************dsiObj->videoSizeCfg.vact: 720***************
    [MCU2_0]     16.143277 s: ******************dsiObj->videoSizeCfg.vfp: 82***************
    [MCU2_0]     16.143315 s: ******************dsiObj->videoSizeCfg.vbp: 63***************
    [MCU2_0]     16.143357 s: ******************dsiObj->videoSizeCfg.vsa: 10***************
    [MCU2_0]     16.143395 s: ******************dsiObj->videoSizeCfg.hsa: 1***************
    [MCU2_0]     16.143432 s: ******************dsiObj->videoSizeCfg.hbp: 3***************
    [MCU2_0]     16.143470 s: ******************dsiObj->videoSizeCfg.rgb: 3840***************
    [MCU2_0]     16.143509 s: ******************dsiObj->videoSizeCfg.hfp: 24***************
    [MCU2_0]     16.143550 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 3879***************
    [MCU2_0]     16.143579 s: 
    [MCU2_0]     16.143599 s: ******************mInfo.vfp: 82***************
    [MCU2_0]     16.143630 s: ******************mInfo.vbp: 63***************
    [MCU2_0]     16.143661 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     16.143692 s: ******************mInfo.hsa: 5***************
    [MCU2_0]     16.143723 s: ******************mInfo.hbp: 5***************
    [MCU2_0]     16.143754 s: ******************mInfo.hfp: 10***************
    [MCU2_0]     16.143788 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     16.143826 s: DSITX_SetVideoSize status 0 
    [MCU2_0]     16.143866 s: ***********************vidMode->burstMode in setter: false***********************
    [MCU2_0]     16.143915 s: ***********************vidMode->syncPulseActive in setter: true***********************
    [MCU2_0]     16.143955 s: DSITX_SetVideoMode status 0 
    [MCU2_0]     16.143976 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 591: 
    [MCU2_0]     16.143998 s: status value9: 0
    [MCU2_0]     16.144037 s: ***********************config->dispEotGen u getter: false***********************
    [MCU2_0]     16.144085 s: ***********************config->hostEotGen u getter: false***********************
    [MCU2_0]     16.144135 s: ***********************config->dispEotGen in setter: false***********************
    [MCU2_0]     16.144182 s: ***********************config->hostEotGen in setter: false***********************
    [MCU2_0]     16.144238 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 597: 
    [MCU2_0]     16.144261 s: status value10: 0
    [MCU2_0]     16.144282 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 603: 
    [MCU2_0]     16.144305 s: status value11: 0
    [MCU2_0]     16.144324 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1161: 
    [MCU2_0]     16.144346 s: Retval value1: 0

    We hae also tested serializer pattern with these params, to double check that other part of the line is OK, and it works.

    Regards,

    Milena

  • Hello Milena,

    One strange thing i noticed in your dump is dsiObj->videoSizeCfg.vfp is set to mInfo.vfp, which is incorrect. Seems you are using DSS_DSI_CONNECTION_DSI2DP_BRIDGE, can you please make sure that connectedTo flag is not set to DSS_DSI_CONNECTION_DSI2DP_BRIDGE in Dss_dctrlDrvEnableVideoDSI API and try out this experiment? This can be controlled from the application also, by setting drvInitParams.dsiInitParams.isConnectedTo flag.. 

    Regards,

    Brijesh

  • Hi Brijesh,

    The only thing that is done under this flag, as far as I see is the assignment of the dsiObj->videoSizeCfg.vfp (to be mInfo.vfp or 1).

    Please correct me If I am wrong. I have commented out in driver all under this define, and tested.Not sure if anywhere else this is used.

    Behavior is same as earlier.

    Note that I have not changed timings for vfp on serializer. Should I do that?

    Or generally change timings such that vfp is 1?

    [MCU2_0]     14.804882 s: DSS: SoC init ... Done !!!
    [MCU2_0]     14.804900 s: DSS: Board init ... !!!
    [MCU2_0]     14.804918 s: DSS: Configuring LA080WH1 Display!
    [MCU2_0]     17.019797 s: DSS: Configuring LA080WH1 Done !!!
    [MCU2_0]     17.019832 s: DSS: Configuring MAX96755F Serializer!
    [MCU2_0]     17.030125 s: DSS: Configuring MAX96755F Done !!!
    [MCU2_0]     17.034844 s: DSS: Board init ... Done !!!
    [MCU2_0]     17.035687 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     17.035741 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     17.035784 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0]     17.035879 s: **********************lane_speed: 409500*******************
    [MCU2_0]     17.035921 s: **********************refClkKHz: 26000*******************
    [MCU2_0]     17.035959 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0]     17.035997 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0]     17.036039 s: **********************tempResult: 252*******************
    [MCU2_0]     17.036077 s: **********************dsiObj->dphyTxFbDiv: 252*******************
    [MCU2_0]     17.036254 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1157: 
    [MCU2_0]     17.036282 s: Should enter here
    [MCU2_0]     17.036315 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 542: 
    [MCU2_0]     17.036338 s: status value1: 0
    [MCU2_0]     17.036364 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 549: 
    [MCU2_0]     17.036387 s: status value2: 0
    [MCU2_0]     17.036412 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 555: 
    [MCU2_0]     17.036435 s: status value3: 0
    [MCU2_0]     17.036463 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 561: 
    [MCU2_0]     17.036485 s: status value4: 0
    [MCU2_0]     17.036651 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 567: 
    [MCU2_0]     17.036673 s: status value5: 0
    [MCU2_0]     17.036694 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 573: 
    [MCU2_0]     17.036716 s: status value6: 0
    [MCU2_0]     17.036740 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 579: 
    [MCU2_0]     17.036763 s: status value7: 0
    [MCU2_0]     17.036787 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 585: 
    [MCU2_0]     17.036810 s: status value8: 0
    [MCU2_0]     17.036850 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     17.036895 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     17.036942 s: ***********************vidMode->syncPulseActive in getter: false***********************
    [MCU2_0]     17.036991 s: ***********************vidMode->burstMode u getter: false***********************
    [MCU2_0]     17.037027 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     17.037063 s: ******************mInfo.vfp: 82***************
    [MCU2_0]     17.037095 s: ******************mInfo.vbp: 63***************
    [MCU2_0]     17.037127 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     17.037158 s: ******************mInfo.hsa: 5***************
    [MCU2_0]     17.037190 s: ******************mInfo.hbp: 5***************
    [MCU2_0]     17.037222 s: ******************mInfo.hfp: 10***************
    [MCU2_0]     17.037257 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     17.037285 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     17.037323 s: ******************horzTotal: 1300***************
    [MCU2_0]     17.037358 s: ******************dsiObj->videoSizeCfg.vact: 720***************
    [MCU2_0]     17.037397 s: ******************dsiObj->videoSizeCfg.vfp: 1***************
    [MCU2_0]     17.037435 s: ******************dsiObj->videoSizeCfg.vbp: 63***************
    [MCU2_0]     17.037473 s: ******************dsiObj->videoSizeCfg.vsa: 10***************
    [MCU2_0]     17.037515 s: ******************dsiObj->videoSizeCfg.hsa: 1***************
    [MCU2_0]     17.037552 s: ******************dsiObj->videoSizeCfg.hbp: 3***************
    [MCU2_0]     17.037590 s: ******************dsiObj->videoSizeCfg.rgb: 3840***************
    [MCU2_0]     17.037628 s: ******************dsiObj->videoSizeCfg.hfp: 24***************
    [MCU2_0]     17.037669 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 3879***************
    [MCU2_0]     17.037697 s: 
    [MCU2_0]     17.037718 s: ******************mInfo.vfp: 82***************
    [MCU2_0]     17.037748 s: ******************mInfo.vbp: 63***************
    [MCU2_0]     17.037779 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     17.037810 s: ******************mInfo.hsa: 5***************
    [MCU2_0]     17.037841 s: ******************mInfo.hbp: 5***************
    [MCU2_0]     17.037872 s: ******************mInfo.hfp: 10***************
    [MCU2_0]     17.037905 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     17.037946 s: DSITX_SetVideoSize status 0 
    [MCU2_0]     17.037987 s: ***********************vidMode->burstMode in setter: false***********************
    [MCU2_0]     17.038036 s: ***********************vidMode->syncPulseActive in setter: true***********************
    [MCU2_0]     17.038076 s: DSITX_SetVideoMode status 0 
    [MCU2_0]     17.038096 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 591: 
    [MCU2_0]     17.038118 s: status value9: 0
    [MCU2_0]     17.038156 s: ***********************config->dispEotGen u getter: false***********************
    [MCU2_0]     17.038203 s: ***********************config->hostEotGen u getter: false***********************
    [MCU2_0]     17.038255 s: ***********************config->dispEotGen in setter: false***********************
    [MCU2_0]     17.038304 s: ***********************config->hostEotGen in setter: false***********************
    [MCU2_0]     17.038359 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 597: 
    [MCU2_0]     17.038382 s: status value10: 0
    [MCU2_0]     17.038403 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 603: 
    [MCU2_0]     17.038425 s: status value11: 0
    [MCU2_0]     17.038444 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1161: 
    [MCU2_0]     17.038467 s: Retval value1: 0
    [MCU2_0]     17.043263 s: DSS: Init ... Done !!!

    Best regards,

    Milena

  • Hello Milena,

    Instead of removing this code, can you please try passing drvInitParams.dsiInitParams.isConnectedTo flag correctly? It shouldn't be set to DSS_DSI_CONNECTION_DSI2DP_BRIDGE. Lets see if it helps. 

    Regards,

    Brijesh

  • Hello Brijesh,

    I tried as you suggested, but behavior is still same.

    static inline void Dss_dsiInitParamsInit(Dss_DsiInitParams *dsiInitParams)
    {
        if(NULL != dsiInitParams)
        {
            dsiInitParams->isAvailable   = UTRUE;
            dsiInitParams->isConnectedTo = DSS_DSI_CONNECTION_FPD;
        }
    }

    This flag is used only at two places, which I manually modified : for vfp setting and for comparison with supportedBlanks struct.

    Log also for reference:

    [MCU2_0]     14.848337 s: DSS: SoC init ... Done !!!
    [MCU2_0]     14.848359 s: DSS: Board init ... !!!
    [MCU2_0]     14.848376 s: DSS: Configuring LA080WH1 Display!
    [MCU2_0]     17.063398 s: DSS: Configuring LA080WH1 Done !!!
    [MCU2_0]     17.063428 s: DSS: Configuring MAX96755F Serializer!
    [MCU2_0]     17.073722 s: DSS: Configuring MAX96755F Done !!!
    [MCU2_0]     17.078440 s: DSS: Board init ... Done !!!
    [MCU2_0]     17.079273 s: ******************dsiObj->cfgDsiTx.numOfLanes: 4***************
    [MCU2_0]     17.079328 s: ******************dsiObj->privDsiTx.numOfLanes: 4***************
    [MCU2_0]     17.079371 s: ******************dsiObj->dphyTxRate: 231***************
    [MCU2_0]     17.079467 s: **********************lane_speed: 409500*******************
    [MCU2_0]     17.079506 s: **********************refClkKHz: 26000*******************
    [MCU2_0]     17.079544 s: **********************dsiObj->dphyTxIpDiv: 2*******************
    [MCU2_0]     17.079582 s: **********************dsiObj->dphyTxOpDiv: 4*******************
    [MCU2_0]     17.079619 s: **********************tempResult: 252*******************
    [MCU2_0]     17.079661 s: **********************dsiObj->dphyTxFbDiv: 252*******************
    [MCU2_0]     17.079824 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1157: 
    [MCU2_0]     17.079852 s: Should enter here
    [MCU2_0]     17.079882 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 542: 
    [MCU2_0]     17.079906 s: status value1: 0
    [MCU2_0]     17.079930 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 549: 
    [MCU2_0]     17.079953 s: status value2: 0
    [MCU2_0]     17.079979 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 555: 
    [MCU2_0]     17.080002 s: status value3: 0
    [MCU2_0]     17.080031 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 561: 
    [MCU2_0]     17.080055 s: status value4: 0
    [MCU2_0]     17.080219 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 567: 
    [MCU2_0]     17.080242 s: status value5: 0
    [MCU2_0]     17.080265 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 573: 
    [MCU2_0]     17.080287 s: status value6: 0
    [MCU2_0]     17.080313 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 579: 
    [MCU2_0]     17.080336 s: status value7: 0
    [MCU2_0]     17.080356 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 585: 
    [MCU2_0]     17.080384 s: status value8: 0
    [MCU2_0]     17.080426 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     17.080473 s: ********************DSITX_VideoBlankingMode *enumVal: 0 ********************
    [MCU2_0]     17.080521 s: ***********************vidMode->syncPulseActive in getter: false***********************
    [MCU2_0]     17.080569 s: ***********************vidMode->burstMode u getter: false***********************
    [MCU2_0]     17.080605 s: **********************dssDctrlUpdateVideoModeConfig***************
    [MCU2_0]     17.080641 s: ******************mInfo.vfp: 82***************
    [MCU2_0]     17.080672 s: ******************mInfo.vbp: 63***************
    [MCU2_0]     17.080704 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     17.080735 s: ******************mInfo.hsa: 5***************
    [MCU2_0]     17.080766 s: ******************mInfo.hbp: 5***************
    [MCU2_0]     17.080797 s: ******************mInfo.hfp: 10***************
    [MCU2_0]     17.080833 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     17.080861 s: **********************dssDctrlUpdateVideoSizeConfig***************
    [MCU2_0]     17.080897 s: ******************horzTotal: 1300***************
    [MCU2_0]     17.080932 s: ******************dsiObj->videoSizeCfg.vact: 720***************
    [MCU2_0]     17.080971 s: ******************dsiObj->videoSizeCfg.vfp: 1***************
    [MCU2_0]     17.081009 s: ******************dsiObj->videoSizeCfg.vbp: 63***************
    [MCU2_0]     17.081047 s: ******************dsiObj->videoSizeCfg.vsa: 10***************
    [MCU2_0]     17.081085 s: ******************dsiObj->videoSizeCfg.hsa: 1***************
    [MCU2_0]     17.081126 s: ******************dsiObj->videoSizeCfg.hbp: 3***************
    [MCU2_0]     17.081164 s: ******************dsiObj->videoSizeCfg.rgb: 3840***************
    [MCU2_0]     17.081202 s: ******************dsiObj->videoSizeCfg.hfp: 24***************
    [MCU2_0]     17.081243 s: ******************dsiObj->videoSizeCfg.blkLinePulsePacket: 3879***************
    [MCU2_0]     17.081271 s: 
    [MCU2_0]     17.081292 s: ******************mInfo.vfp: 82***************
    [MCU2_0]     17.081323 s: ******************mInfo.vbp: 63***************
    [MCU2_0]     17.081354 s: ******************mInfo.vsa: 10***************
    [MCU2_0]     17.081385 s: ******************mInfo.hsa: 5***************
    [MCU2_0]     17.081416 s: ******************mInfo.hbp: 5***************
    [MCU2_0]     17.081447 s: ******************mInfo.hfp: 10***************
    [MCU2_0]     17.081480 s: ******************mInfo.pixelClock: 68250000***************
    [MCU2_0]     17.081520 s: DSITX_SetVideoSize status 0 
    [MCU2_0]     17.081559 s: ***********************vidMode->burstMode in setter: false***********************
    [MCU2_0]     17.081608 s: ***********************vidMode->syncPulseActive in setter: true***********************
    [MCU2_0]     17.081650 s: DSITX_SetVideoMode status 0 
    [MCU2_0]     17.081670 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 591: 
    [MCU2_0]     17.081692 s: status value9: 0
    [MCU2_0]     17.081732 s: ***********************config->dispEotGen u getter: false***********************
    [MCU2_0]     17.081778 s: ***********************config->hostEotGen u getter: false***********************
    [MCU2_0]     17.081828 s: ***********************config->dispEotGen in setter: false***********************
    [MCU2_0]     17.081879 s: ***********************config->hostEotGen in setter: false***********************
    [MCU2_0]     17.081936 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 597: 
    [MCU2_0]     17.081959 s: status value10: 0
    [MCU2_0]     17.081983 s: src/drv/dctrl/dss_dctrlDsi.c @ Line 603: 
    [MCU2_0]     17.082005 s: status value11: 0
    [MCU2_0]     17.082024 s: src/drv/dctrl/dss_dctrlApi.c @ Line 1161: 
    [MCU2_0]     17.082046 s: Retval value1: 0
    [MCU2_0]     17.086837 s: DSS: Init ... Done !!!

    Also, I have noticed that after the boot, and before the run_app_single_cam we already have value 0x04 of register 0x048000F0 .

    And it stays at same value during the use case execution.

    Regards,

    Milena

  • Hello Brijesh,

    For the above tests we used polarity HIGH (both tda4 and ser)

    vpParams.hsPolarity = APP_DCTRL_POL_HIGH;
    vpParams.vsPolarity = APP_DCTRL_POL_HIGH;

    When we changed polarity to  LOW on both ser and tda4, it started working :) 

    vpParams.hsPolarity = APP_DCTRL_POL_LOW;
    vpParams.vsPolarity = APP_DCTRL_POL_LOW;

    It works both, for the vfp 1 (disabled DSS_DSI_CONNECTION_DSI2DP_BRIDGE ) and vfp 82 .

    Does TDA4H supports VS and HS HIGH polarity?

    Best regards,

    Milena

  • Hi Milena,

    That's great news. 

    Well, TDA4 supports both the polarity, but this polarity is between DSS and DSI and the default polarity given in the sample example should have worked. isn't it? Are you not using default example ? 

    Regards,

    Brijesh

  • Hi Brijesh,

    Low polarity is default one.. 

    During the debugging, we tested both low and high, but none worked, and for the last tests high polarity remained in the code.

    Will check tomorrow which of the last changes, actually made it work, apart from the polarity.

    Regards,

    Milena

  • Hi Brijesh, 

    We have also tested with 20MHz crystal. It works as well (of course with the params for the 20Mhz refClk).

    Milena

  • That's great. Closing this thread.