[FAQ] AM62L ( AM62L32 , AM62L31 ) Custom board hardware design – I2C interface

Kallikuppa Sreenivasa

Guru**** 225425 points

Part Number: AM62L

Tool/software:

Hi TI Experts,

I have the below queries regarding the I2C interface

Need information on the number of I2C interfaces available
Termination of I2C interfaces when used as I2C interface and not used as I2C interface.
Any additional recommendations / Guidelines
Any concerns on Interfacing SoC Non-Failsafe I2C to devices that are powered before the SoC- Ex PMIC
Any exception that are required to be considered when using the I2C interfaces.
Can the I2C interface be used to interface with devices supporting SMBus or PMBus

Let me know your thoughts.

Unused iOs connection

(+) [FAQ] What should be done with unused I/O pins of the level translator devices? - Logic forum - Logic - TI E2E support forums

over 1 year ago

0 Kallikuppa Sreenivasa over 1 year ago

TI__Guru**** 225425 points

Hi Board designers,

Refer below inputs:

1. Need information on the number of I2C interfaces available

MAIN Domain: There are 4 instances I2C0, I2C1, I2C2, I2C3

WKUP Domain: WKUP_I2C0

2.Termination of I2C interfaces when used as I2C interface and not used as I2C interface.

For I2C interfaces with open-drain output type buffer (I2C2), an external pull is recommended, when the IO is used.

3.Any additional recommendations / Guidelines

The following I2C (I2C2, I2C3) instances implements IOSET. Make sure the usage of the correct IOSET in the custom design.
Timing closure is based on the IOSETs.

4.Any concerns on Interfacing SoC Non-Failsafe I2C to devices that are powered before the SoC - Ex PMIC

Are the attached PMIC IOs true open-drain I2C IOs? If so, are the pull-up resistors associated with this I2C port powered by the same power supply that is used to power SoC I2C Example I2C0 IOs? We should not have a fail-safe problem if the answer to both questions is yes.

Is there anything else connected to these I2C signals that could source a potential to the I2C0 pins before the IOs are powered?

We are only concerned with fail-safe if there is a possibility for the attached devices to apply a potential to the SoC IOs before they receive power. We do not have any fail-safe concern if that is not possible.

5.Any exception that are required to be considered when using the I2C interfaces.

Refer section

6.11.5.12 I2C
The device contains five multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was
designed to be compliant to the Philips I2C-bus specification version 2.1. However, the device IOs are not
fully compliant to the I2C electrical specification. The speeds supported and exceptions are described per port
below:

Read through the Exceptions section for I2C0, I2C1, I2C2, and I2C3 + Exceptions section for WKUP_I2C0

6.Can the I2C interface be used to interface with devices supporting SMBus or PMBus

The I2C module implemented in these processor families does not support SM Bus or PM Bus

7. RC delay when open drain output type I2C interface is pulled to 3.3V

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 1 year ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 225425 points

Hi Board designers,

Additional reference.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1220150/faq-am625-am623-am625sip-am625-q1-am620-q1-custom-board-hardware-design-i2c-interface

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 1 year ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 225425 points

Hi Board designers,

Refer below regarding I2C clock stretching

https://www.ti.com/lit/an/sbaa565/sbaa565.pd

6.2 Clock Stretching In some I2C target devices, there are situations that the target device controls the SCL serial clock. In those cases, the target device can slow down the communication. This process is known as clock stretching. In general, the SCL line and therefore the I2C clock rate, is controlled by the controller. However, there are instances where the target device is unable to comply with the clock rate. For example, the target device requires extra time to process a command or send data. In such cases, the target device can slow down the communication through clock stretching.