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TDA4VE-Q1: Questions about UART1 SM implementation

Taehong Kim
Intellectual 385 points

Part Number: TDA4VE-Q1

Tool/software:

Dear TI experts,

I've investigated and implemented UART1 SM mentioned in safety manual as below.



When I search related apis in pdk, I've found UART_procLineStatusErr api in UART_v1.c is the answer.

It seems like it checks UART's LSR_UART(we do not use CIR and IRDA) register and detects break, parity, framing and overrun errors.

So, I'm also trying to implement the api checks periodically checks LSR register.

Q1. Is my investigation and plan right? is there any other status register need to be checked for this SM?

Q2. I saw this LSR register has 'trasmit hold' not empty status for 5 and 6 bit position. I think this bit is almost always 'set' because of lots of uart messages printed out.
So, I'll exclude this bit status check for UART1 SM implementation. Could you explain detail about this bit meaning?

Thanks,
Taehong Kim

  • +1
    TI__Mastermind 22680 points

    Hi Taehong,

    Yes, the UART_LSR register is the main register for UART line status and understanding the errors. Additionally, you can take a look at UART_RHR register as well to see the specific errors in a character.

    Please take a look at this snippet from the TRM:

    Taehong Kim said:
    So, I'll exclude this bit status check for UART1 SM implementation. Could you explain detail about this bit meaning?

    You are mainly correct about UART_LSR_UART[5] and UART_LSR_UART[6] that they hold whether the transmit hold register or TX FIFO and shift registers are empty or not. However, this register will not take into account if the transmission is complete or not so this may be the reason it seems almost always 'set'.

    Thanks,

    Neehar