Tool/software:
We have the SPI4 connected to the FPGA and I need to download its RBF file.
I carefully studied the article:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/496527/how-to-enable-mcspi-clk-in-kernel
and reproduced exactly what is written there except the MODE_MANUAL macro in pin definitions which I wasn't able to find throught the whole Linux source tree.
But the results are a bit unexpected
1. The spi4_clk pin acts as required. I see the clocks on the scope and they correspond to the defined speed. If I change the speed the clocks follow the change.|
But the data line spi4_d0 remains high all the time independently of what is transmitted.
I checked that it is connected correctly by changing MUX register values - works fine.
I checked this also by redefining this pin as GPIO - works fine.
2. An attempt to read the MCSPI4 registers fails - kernel throughs crash report. In this connection I have the following question:
The reference manual gives the following addresses of the MCSPI_CHxCONF registers:
0x4809 812C + (0x14 * x) McSPI1
0x4809 A12C + (0x14 * x) McSPI2
0x480B 812C + (0x14 * x) McSPI3
0x480B A12C + (0x14 * x) McSPI4
Is this correct? If each McSPI has its own different(!) base address why do we need the 0x14*x additional offset? And why do I have the crash on reading(!) the MCSPI registers?
Thank you very much for any hint.
