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TDA4VM: CPSW2G: Tx Priority queues

Hasan Aarzoo
Intellectual 485 points
Part Number: TDA4VM

Tool/software:

Hi TI,

I am developing my own cpsw2g driver using bare metal.

I have a few questions about CPSW2G Tx Priority queues which are as follows:

  1. What are Tx Priority queues?

  2. How are they allocated inside MAC Port FIFO?
    Are these HW components and physically mapped inside MAC Port FIFO?

  3. Who is responsible for putting the data in Tx Priority queues from MAC Port Tx FIFO?

  4. Consider a case that I have allocated 16 KB for Tx MAC Port Buffer. and I have allocated 2KB for Tx Priority queue 0.
    Is the remaining size allocated for Tx MAC Port Buffer is now 14 KB (16 KB - 2 KB) or Tx MAC Port Buffer is still 16 KB and it is not related to the size of Tx Priority queues?

 

Looking forward to hearing back from you.

Best Regards,
Hasan

  • 0
    TI__Guru 65270 points

    Hi,

    Hasan Aarzoo said:
    What are Tx Priority queues?

    As informed in below thread, Tx priority Queues are queues to hold the different traffic priority packets.
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1475124/tda4vm-cpsw2g-fifos/5674172?tisearch=e2e-sitesearch&keymatch=CPSW2G%20FIFO#5674172

    Hasan Aarzoo said:
    How are they allocated inside MAC Port FIFO?
    Are these HW components and physically mapped inside MAC Port FIFO?

    These queues are internal H/W memory to manage the Tx packets of various traffic from MAC Port.

    Hasan Aarzoo said:
    Who is responsible for putting the data in Tx Priority queues from MAC Port Tx FIFO?

    Host Port will copy the packets into Tx priority queues of MAC Port as per packet priority received to Host Port.

    Hasan Aarzoo said:
    Consider a case that I have allocated 16 KB for Tx MAC Port Buffer. and I have allocated 2KB for Tx Priority queue 0.
    Is the remaining size allocated for Tx MAC Port Buffer is now 14 KB (16 KB - 2 KB) or Tx MAC Port Buffer is still 16 KB and it is not related to the size of Tx Priority queues?

    Tx MAC Port buffer is 16KB, CPSW don't have individual configuration of queue for each priority as mentioned in E2E specified above.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 485 points

    Hi Sudheer,

    Doredla Sudheer Kumar said:
    Host Port will copy the packets into Tx priority queues of MAC Port as per packet priority received to Host Port.

    How will Host port copy the packets into Tx priority queue of MAC Port? Is there any transmit scheduler which copies the data from Host Port Rx (Ingress) FIFO buffer to MAC Port's Transmit priority queues?

    Doredla Sudheer Kumar said:
    These queues are internal H/W memory to manage the Tx packets of various traffic from MAC Port.

    Are these internal HW memories located inside Tx MAC Port Buffer?

    How 16 KB of  Tx MAC Port Buffer is distributed across Tx Priority queues (0-7)? Is my understanding shown below with the help of diagram correct about distribution of Tx MAC Port Buffer is distributed across Tx Priority queues (0-7)?



    Doredla Sudheer Kumar said:
    These queues are internal H/W memory

    What is the size of these internal HW Memories for each queue(0-7)? Is the size fixed or can be configured?

    Best regards,
    Hasan

  • 0 in reply to Hasan Aarzoo
    TI__Guru 65270 points

    Hi,

    Hasan Aarzoo said:
    Doredla Sudheer Kumar said:
    Host Port will copy the packets into Tx priority queues of MAC Port as per packet priority received to Host Port.

    How will Host port copy the packets into Tx priority queue of MAC Port? Is there any transmit scheduler which copies the data from Host Port Rx (Ingress) FIFO buffer to MAC Port's Transmit priority queues?

    Ingress data into Host Port Rx FIFO will be forwarded to External Port Tx FIFO based on ALE forwarding rules.
    As per ingress packet priority CPSW will forward the packet to External Port Tx FIFO (priority Queue).

    Hasan Aarzoo said:
    How 16 KB of  Tx MAC Port Buffer is distributed across Tx Priority queues (0-7)? Is my understanding shown below with the help of diagram correct about distribution of Tx MAC Port Buffer is distributed across Tx Priority queues (0-7)?

    Yes. your understanding is correct.

    Hasan Aarzoo said:
    These queues are internal H/W memory

    What is the size of these internal HW Memories for each queue(0-7)? Is the size fixed or can be configured?

    These will be managed with the TXFIFO size allocated per Port.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 485 points

    Hi Sudheer

    Doredla Sudheer Kumar said:
    How 16 KB of  Tx MAC Port Buffer is distributed across Tx Priority queues (0-7)? Is my understanding shown below with the help of diagram correct about distribution of Tx MAC Port Buffer is distributed across Tx Priority queues (0-7)?

    Yes. your understanding is correct.

    Another question,

    Consider a case where I have a similar memory distribution for MAC Port Tx FIFO and Tx Priority queues (0-7).
    I am only transmitting non-Vlan tagged packets and CPSW is in VLAN Unaware mode .

    Based on my understanding only Tx Priority queues 0 will be used for all the transfers. Tx Priority queues 1-7 will not be used at all for the my transfers.

    In that case memory allocated for  Tx Priority queues 1-7  in MAC Port Tx FIFO will remain unused.

    Is my undersatning correct?

    Best regards,

    Hasan

  • +1 in reply to Hasan Aarzoo
    TI__Guru 65270 points

    Hi,

    Hasan Aarzoo said:

    Consider a case where I have a similar memory distribution for MAC Port Tx FIFO and Tx Priority queues (0-7).
    I am only transmitting non-Vlan tagged packets and CPSW is in VLAN Unaware mode .

    Based on my understanding only Tx Priority queues 0 will be used for all the transfers. Tx Priority queues 1-7 will not be used at all for the my transfers.

    In that case memory allocated for  Tx Priority queues 1-7  in MAC Port Tx FIFO will remain unused.

    Is my undersatning correct?

    Yes, memory reserved for Priority Queues 1-7 are unused in your case.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 485 points

    Hi Sudheer,

    Consider a case where I have a similar memory distribution for MAC Port Tx FIFO and Tx Priority queues (0-7).
    I am only transmitting non-Vlan tagged packets and CPSW is in VLAN Unaware mode .

    Is it possible that I can fill the the data one by one in priority queues 0-7 and data from the MAC Port Tx FIFO buffer is transmitted in first in and first out order rather than using the priority of transmit queues?

    Best regards,
    Hasan

  • 0 in reply to Hasan Aarzoo
    TI__Guru 65270 points

    Hi,

    Hasan Aarzoo said:
    Is it possible that I can fill the the data one by one in priority queues 0-7 and data from the MAC Port Tx FIFO buffer is transmitted in first in and first out order rather than using the priority of transmit queues?

    No, it is internal H/W operation, it is not possible to send same priority packets to different Tx priority queues.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 485 points

    Hi Sudheer,

    As previously discussed, CPSW2G supports 8 Tx Udma channels and 1 Rx Udma channel.

    1. Are these 8 Tx Udma channels somehow related to priority queues 0-7? If yes, how?

    2. Are these 8 Tx Udma channels are not related to priority queues 0-7?
    3. Can you please explain me a use case where all 8 Udma Tx channel are used to communicate with CPSW where all transmitted ethernet packets are  non-VLAN tagged packets?

    4. Can you please explain me a use case where all 8 Udma Tx channel are used to communicate with CPSW where all transmitted ethernet packets are  VLAN tagged packets?

    Best regards,
    Hasan

  • +1 in reply to Hasan Aarzoo
    TI__Guru 65270 points

    Hi,

    Hasan Aarzoo said:

    1. Are these 8 Tx Udma channels somehow related to priority queues 0-7? If yes, how?

    No

    Hasan Aarzoo said:

    • Are these 8 Tx Udma channels are not related to priority queues 0-7?

    Yes, these are not related to priority queues.

    Hasan Aarzoo said:
    Can you please explain me a use case where all 8 Udma Tx channel are used to communicate with CPSW where all transmitted ethernet packets are  non-VLAN tagged packets?

    In RTOS examples, we are not enabling 8 Tx channels.
    Only 1 channel is enabled.

    In case of Linux you can have multiple channels and map to Kernel SW Queues it allows more bandwidth to send traffic to driver.
    Also, Linux has tc concept to map to priority to SW queues and send different traffic data on each of sw queues.

    Hasan Aarzoo said:
    Can you please explain me a use case where all 8 Udma Tx channel are used to communicate with CPSW where all transmitted ethernet packets are  VLAN tagged packets?

    All will land in same Host Rx FIFO, and forwarded to External Port tx FIFO to different priority queue.

    All is depends upon customer use-cases CPSW H/W has capability to have 8 Tx channels.

    If you have any queries relate to your specific use-case, please create a new thread if any queries.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 485 points

    Hi Sudheer,

    Thank you for the information.

    If I have questions about specific use cases then as suggested I will create a new thread.

    Best regards,
    Hasan