Hi All ,
In the TMS320C6678 EVM it is mentioned that the clock inputs (ex. DDRCLK,SYSCLK,PCIeCLK etc) should not be driven untill CVDD is valid and they can be driven anytime after CVDD is valid and before 16usec from deasserting the RESET signal.
In our custom board we are sourcuing the PCIe,SRIO,MCM clock inputs to TMS320C6678 via CDCE62005 chip. The CDCE chip needs programming to generate the clocks.In our board the chip gets programmed via a host processor over SPI interface. Once CVDD is valid the host processor programms the CDCE chip to generate the clocks. This process is expected to take a couple of seconds time. Therefore , in our board , once CVDD is valid the clocks(PCIe,SRIO,MCM ) are generated after a couple of seconds. Until then they are maintained in high impedance state. Will it cause any issues if the clcoks are kept in high impedance state for a long time (5-10 secs) after CVDD is valid ? There is a statement in datasheet that reads
"To avoid internal oscillation the clock inputs should be removed from the high impedance state shortly after CVDD is present." How long can the clocks be held in high impedance after CVDD is valid to ensure safe operation ? -Anil
