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Original question:

DRA829V: [EP2000][Main2_0] : ETHFW RTOS SDK 10.1 : Need to receive any data from MAC interface regardless of MAC addr or...

DRA829V: [EP2000][Main2_0] : SGMII PORTS were not able to bringup 10.1 PSDK when linux is also 10.1

satyanandam gadde
Prodigy 110 points
Part Number: DRA829V

Tool/software:

Hello TI,

           When we have Old Linux SDK (7.3) we upgraded to 10.1 RTOS SDK for MCU2_0 and MCU2_1 there everything working fine, but when we upgraded to new Linux SDK (10.1), we see that SGMII ports not able to initialize, so what could be the issue ?

Thanks and Regards,

Satya. 

  • 0
    TI__Guru 65170 points

    Hi,

    Can you please check SerDes configuration is taken care in latest SDK as similar to old SDK.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 110 points

    Hi Sudheer,

         yes Configuration is good, same MCU2_0 image is working fine when i was working with old linux SDK, now we are upgrading to new Linux image (10.1), then issue observed, what could be the Linux image impact for SGMII PORTs ?

  • 0 in reply to satyanandam gadde
    Prodigy 110 points

    Hi Sudheer,

          if i call Board_CfgSGMII function core freeze happening, if i disable this function call then other functionalities are working but SGMII ports were down,

    Regards

    satya. 

  • 0 in reply to satyanandam gadde
    TI__Guru 65170 points

    Hi,

    satyanandam gadde said:
    if i call Board_CfgSGMII function core freeze happening, if i disable this function call then other functionalities are working but SGMII ports were down,

    Default u-boot stage SerDes is enabled in SDK.
    Please check what are changes made in u-boot and Linux related to SerDes during SDK 7.3 and adopt the same to latest SDK.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 180 points

    From Linux side, in SDK 7.3, we didn't change any config except below, we did the same in the SDK10. 
    &davinci_mdio {
            phy0: ethernet-phy@0 {
                    reg = <0>;
    -               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
    +               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
                    ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 110 points

    Hi Sudheer,

          Also observed that whenever we tried to access the base address CSL_SERDES_10G0_BASE then core was freeze means is it something related to access issue or MPU issue, if yes how can we solve this ?

    #define CSL_SERDES_10G0_BASE             (0x5050000UL) )

    From the below Image which function is accessing this address that time software stuck there. 

    Regards,

    Satya. 

  • 0 in reply to satyanandam gadde
    TI__Guru 65170 points

    Hi,

    satyanandam gadde said:

        Also observed that whenever we tried to access the base address CSL_SERDES_10G0_BASE then core was freeze means is it something related to access issue or MPU issue, if yes how can we solve this ?

    #define CSL_SERDES_10G0_BASE             (0x5050000UL) )

    It means SerDes Modules is not enabled.

    Can you please confirm have you updated ethfw/utils/board/src/j721e/board_j721e_evm.c file with the required SerDes configuration like clock configuration and power on the module?

    Please cross with changes made in SDK 7.3.

    Best Regards,
    Sudheer

  • +1 in reply to Doredla Sudheer Kumar
    Prodigy 110 points

    Hello Sudheer,

            I have enabled the clock and Serdes 10G0 like below then looks like working fine

    Board_en_SERDES4_and_refClk function calling before Board_CfgSgmii call

    static Board_STATUS Board_en_SERDES4_and_refClk(void)
    {
    uint64_t clkRateHz = 100000000U, clkRateRead = 0U;
    uint32_t moduleId = TISCI_DEV_SERDES_10G0;
    int32_t i, result;
    uint32_t clkID[] = { TISCI_DEV_SERDES_10G0_CORE_REF_CLK };
    uint32_t parentID[] = { TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK };

    uint32_t moduleState;
    uint32_t resetState;
    uint32_t contextLossState;

    int32_t ret = Sciclient_pmGetModuleState(TISCI_DEV_SERDES_10G0, &moduleState,
    &resetState, &contextLossState,SCICLIENT_SERVICE_WAIT_FOREVER);

    /* Set module to ON state */
    if ( (ret == CSL_PASS) && (moduleState == 0U) )
    {
    Sciclient_pmSetModuleState(TISCI_DEV_SERDES_10G0,
    TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
    TISCI_MSG_FLAG_AOP,
    SCICLIENT_SERVICE_WAIT_FOREVER);
    }
    else
    {
    }

    for(i = 0; i < (sizeof(clkID)/sizeof(clkID[0])); i++)
    {
    /* Disable the clock */
    result = Sciclient_pmModuleClkRequest(moduleId,
    clkID[i],
    TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ,
    0U,
    SCICLIENT_SERVICE_WAIT_FOREVER);
    if (CSL_SERDES_NO_ERR != result)
    {
    return BOARD_FAIL;
    }

    /* Set the parent */
    result = Sciclient_pmSetModuleClkParent(moduleId,
    clkID[i],
    parentID[i],
    SCICLIENT_SERVICE_WAIT_FOREVER);

    if (CSL_SERDES_NO_ERR != result)
    {
    return BOARD_FAIL;
    }

    /* Set the clock at the desirable frequency */
    result = Sciclient_pmSetModuleClkFreq(moduleId,
    clkID[i],
    clkRateHz,
    TISCI_MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE,
    SCICLIENT_SERVICE_WAIT_FOREVER);

    if (CSL_SERDES_NO_ERR != result)
    {
    return BOARD_FAIL;
    }

    /* Confirm if clock is set */
    clkRateRead = 0U;
    result = Sciclient_pmGetModuleClkFreq(moduleId,
    clkID[i],
    &clkRateRead,
    SCICLIENT_SERVICE_WAIT_FOREVER);

    if ((CSL_SERDES_NO_ERR != result) || (clkRateRead != clkRateHz))
    {
    return BOARD_FAIL;
    }
    }

    /* Set module to ON state */
    result = Sciclient_pmSetModuleState(moduleId,
    TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
    (TISCI_MSG_FLAG_AOP | TISCI_MSG_FLAG_DEVICE_RESET_ISO),
    SCICLIENT_SERVICE_WAIT_FOREVER);
    if (CSL_SERDES_NO_ERR != result)
    {
    return BOARD_FAIL;
    }

    /* Reset if changed state to enabled */
    result = Sciclient_pmSetModuleRst(moduleId,
    0x0U /*resetBit*/,
    SCICLIENT_SERVICE_WAIT_FOREVER);

    if (CSL_SERDES_NO_ERR != result)
    {
    return BOARD_FAIL;
    }


    return BOARD_SOK;
    }