Tool/software:
Hi,
The "interrupt reentrance" is somewhat similar to "interrupt nesting" where an INT with higher priority can interrupt the response of an INT with lower priority.
In the case of "interrupt reentrance", the response of an INT can be interrupted by itself. Now, taking F28C36 as an example to demonstrate this.
In F28C36, there is a register called as "SYSHNDCTRL", as below:
Through this register, we can implement this function for some INT sources, rather than all INTs. Here, taking PendSV as an example to depict this process.
1) PendSV event occurs (i.e. triggers PendSV INT).
2) The control flow enters the ISR of PendSV.
3) SYSHNDCTRL.PNDSV(bit10) is 1 (Hardware behavior).
4) Doing short-term tasks.
5) Set SYSHNDCTRL.PNDSV(bit10) to be 0 manually.
6) Doing long-term things. (During this period, the ISR of PendSV is reentrant)
7) Set SYSHNDCTRL.PNDSV(bit10) to be 1 (manually)
8) Doing short-term thing.
9) Exiting from ISR.
So during the step 6, the ISR of PENDSV will be reentrant, that is, at this time, if the PendSV event arises, the control flow will reenter the PendSV ISR.
I hope this process can clarify what I want and so-called "interrupt reentrance".
And now, we want to implement "interrupt reentrance" based on AM64x.R5 core, like on F28M36(C2000).
Can you tell me whether AM64x.R5 core supports the "interrupt reentrance" ?
If it is capable, please tell me how to implement it, or supply me some reference materials.
Thanks.
Ethan.
