TMS320C6678 DDR3 PLL Multiplier value

Hi All ,

In my custom board i am using TMS320C6678 device. The DDRCLK input is 100MHz. i am using a 1333 MT/s memory on board. to generate the required 666.667MHz clock for the memory i plan to configure the DDR3 PLL multipler and divide values as descibed below ;

 DDR3PLLCTL0: PLLM = 40

 DDR3PLLCTL0: PLLD = 3

From this is expect teh output clock generated to be 100 * (40/3) *(1/2) = 666.667 MHz.

Can the DDR3 PLL VCO support a multiplier value of 40 ? Does anyone forsee any issue in this combination.

-Anil